cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/verg_4.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: VERG_4.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all;
   8
   9 entity VERG_4 is
  10         port
  11         (
  12                 IN_A :in std_logic_vector(3 downto 0);
  13                 IN_B :in std_logic_vector(3 downto 0);
  14                 GLEICH :out std_logic
  15         );
  16 end entity VERG_4;
  17
  18 architecture VERG_4_DESIGN of VERG_4 is
  19
  20 begin
  21
  22         process (IN_A,IN_B)
  23         begin
  24
  25                 if IN_A = IN_B then
  26                         GLEICH <= '1';
  27                 else
  28                         GLEICH <= '0';
  29                 end if;
  30         end process;
  31
  32 end architecture VERG_4_DESIGN;
  33