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[raggedstone] / ethernet / source / pci / pci_wb_addr_mux.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name "wb_addr_mux.v" ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// ////
11 //// All additional information is avaliable in the README ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_wb_addr_mux.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.1 2003/01/27 16:49:31 mihad
49 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
50 //
51 // Revision 1.4 2002/08/19 16:54:25 mihad
52 // Got rid of undef directives
53 //
54 // Revision 1.3 2002/02/01 15:25:13 mihad
55 // Repaired a few bugs, updated specification, added test bench files and design document
56 //
57 // Revision 1.2 2001/10/05 08:14:30 mihad
58 // Updated all files with inclusion of timescale file for simulation purposes.
59 //
60 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
61 // New project directory structure
62 //
63 //
64
65 // module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
66 `include "pci_constants.v"
67 // synopsys translate_off
68 `include "timescale.v"
69 // synopsys translate_on
70
71 module pci_wb_addr_mux
72 (
73 `ifdef REGISTER_WBS_OUTPUTS
74 clk_in,
75 reset_in,
76 sample_address_in,
77 `endif
78 address_in,
79 bar0_in,
80 bar1_in,
81 bar2_in,
82 bar3_in,
83 bar4_in,
84 bar5_in,
85 am0_in,
86 am1_in,
87 am2_in,
88 am3_in,
89 am4_in,
90 am5_in,
91 ta0_in,
92 ta1_in,
93 ta2_in,
94 ta3_in,
95 ta4_in,
96 ta5_in,
97 at_en_in,
98 hit_out,
99 address_out
100 );
101
102 input [31:0] address_in ;
103 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
104 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
105 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
106 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
107 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
108 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
109 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
110 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
111 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
112 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
113 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
114 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
115 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
116 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
117 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
118 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
119 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
120 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
121 input [5:0] at_en_in ;
122 output [5:0] hit_out ;
123 output [31:0] address_out ;
124 reg [31:0] address_out ;
125
126 wire [31:0] addr0 ;
127 wire [31:0] addr1 ;
128 wire [31:0] addr2 ;
129 wire [31:0] addr3 ;
130 wire [31:0] addr4 ;
131 wire [31:0] addr5 ;
132
133 wire [5:0] hit ;
134 assign hit_out = hit ;
135
136 `ifdef REGISTER_WBS_OUTPUTS
137 input clk_in, reset_in, sample_address_in ;
138
139 reg [31:0] address ;
140 always@(posedge clk_in or posedge reset_in)
141 begin
142 if ( reset_in )
143 address <= #`FF_DELAY 0 ;
144 else
145 if ( sample_address_in )
146 address <= #`FF_DELAY address_in ;
147 end
148 `else
149 wire [31:0] address = address_in ;
150 `endif
151
152 `ifdef GUEST
153 `ifdef NO_CNF_IMAGE
154 `else
155 `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
156 `endif
157 `else
158 `ifdef HOST
159 `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
160 `endif
161 `endif
162
163 `ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
164 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
165 (
166 .hit (hit[0]),
167 .addr_out (addr0),
168 .addr_in (address),
169 .base_addr (bar0_in),
170 .mask_addr (am0_in),
171 .tran_addr (ta0_in),
172 .at_en (1'b0)
173 ) ;
174 `else
175 // configuration image not implemented
176 assign hit[0] = 1'b0 ;
177 assign addr0 = 32'h0000_0000 ;
178 `endif
179
180 // one image is always implemented
181 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
182 (
183 .hit (hit[1]),
184 .addr_out (addr1),
185 .addr_in (address),
186 .base_addr (bar1_in),
187 .mask_addr (am1_in),
188 .tran_addr (ta1_in),
189 .at_en (at_en_in[1])
190 ) ;
191
192 `ifdef WB_IMAGE2
193 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
194 (
195 .hit (hit[2]),
196 .addr_out (addr2),
197 .addr_in (address),
198 .base_addr (bar2_in),
199 .mask_addr (am2_in),
200 .tran_addr (ta2_in),
201 .at_en (at_en_in[2])
202 ) ;
203
204 `else
205 assign hit[2] = 1'b0 ;
206 assign addr2 = 0 ;
207 `endif
208
209 `ifdef WB_IMAGE3
210 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
211 (
212 .hit (hit[3]),
213 .addr_out (addr3),
214 .addr_in (address),
215 .base_addr (bar3_in),
216 .mask_addr (am3_in),
217 .tran_addr (ta3_in),
218 .at_en (at_en_in[3])
219 ) ;
220 `else
221 assign hit[3] = 1'b0 ;
222 assign addr3 = 0 ;
223 `endif
224
225 `ifdef WB_IMAGE4
226 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
227 (
228 .hit (hit[4]),
229 .addr_out (addr4),
230 .addr_in (address),
231 .base_addr (bar4_in),
232 .mask_addr (am4_in),
233 .tran_addr (ta4_in),
234 .at_en (at_en_in[4])
235 ) ;
236 `else
237 assign hit[4] = 1'b0 ;
238 assign addr4 = 0 ;
239 `endif
240
241 `ifdef WB_IMAGE5
242 pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
243 (
244 .hit (hit[5]),
245 .addr_out (addr5),
246 .addr_in (address),
247 .base_addr (bar5_in),
248 .mask_addr (am5_in),
249 .tran_addr (ta5_in),
250 .at_en (at_en_in[5])
251 ) ;
252 `else
253 assign hit[5] = 1'b0 ;
254 assign addr5 = 0 ;
255 `endif
256
257 // address multiplexer
258 always@
259 (
260 hit or
261 addr0 or
262 addr1 or
263 addr2 or
264 addr3 or
265 addr4 or
266 addr5
267 )
268 begin
269 case ( {hit[5:2], hit[0]} )
270 5'b0_0_0_0_1: address_out = addr0 ;
271 5'b0_0_0_1_0: address_out = addr2 ;
272 5'b0_0_1_0_0: address_out = addr3 ;
273 5'b0_1_0_0_0: address_out = addr4 ;
274 5'b1_0_0_0_0: address_out = addr5 ;
275
276 // default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image
277 // this multiplexer can be completely removed during synthesys
278 default: address_out = addr1 ;
279 endcase
280 end
281
282 endmodule
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