cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/Verg_2.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: VERG_2.VHD
   5
   6 library ieee ;
   7 use ieee.std_logic_1164.all ;
   8
   9 entity  VERG_2  is
  10         port
  11         (
  12         IN_A            :in             std_logic_vector(1 downto 0);
  13         IN_B            :in             std_logic_vector(1 downto 0);
  14         GLEICH  :out    std_logic
  15         );
  16 end entity VERG_2 ;
  17
  18 architecture VERG_2_DESIGN of VERG_2 is
  19
  20 begin
  21
  22         process (IN_A,IN_B)
  23         begin
  24
  25                 if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
  26                         else                                                                                    GLEICH  <=      '0';
  27                 end if;
  28
  29         end process;
  30
  31 end architecture VERG_2_DESIGN ;