cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/io_mux_reg.vhd

   1 -- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007
   2
   3
   4
   5 LIBRARY ieee;
   6
   7 USE ieee.std_logic_1164.ALL;
   8 USE ieee.numeric_std.ALL;
   9
  10
  11 entity IO_MUX_REG is
  12         Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
  13                LOAD_ADDR_REG : In std_logic;
  14                PCI_CBEn : In std_logic_vector (3 downto 0);
  15                PCI_CLOCK : In std_logic;
  16                PCI_FRAMEn : In std_logic;
  17                PCI_IDSEL : In std_logic;
  18                PCI_IRDYn : In std_logic;
  19                PCI_PAR : In std_logic;
  20                PCI_RSTn : In std_logic;
  21                READ_SEL : In std_logic_vector (1 downto 0);
  22                USER_DATA : In std_logic_vector (31 downto 0);
  23                PCI_AD : InOut std_logic_vector (31 downto 0);
  24                AD_REG : Out std_logic_vector (31 downto 0);
  25                ADDR_REG : Out std_logic_vector (31 downto 0);
  26                CBE_REGn : Out std_logic_vector (3 downto 0);
  27                FRAME_REGn : Out std_logic;
  28                IDSEL_REG : Out std_logic;
  29                IRDY_REGn : Out std_logic;
  30                PAR_REG : Out std_logic );
  31 end IO_MUX_REG;
  32
  33 architecture SCHEMATIC of IO_MUX_REG is
  34
  35         SIGNAL gnd : std_logic := '0';
  36         SIGNAL vcc : std_logic := '1';
  37
  38         signal IO_DATA : std_logic_vector (31 downto 0);
  39         signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
  40
  41         component ADDRESS_REGISTER
  42                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  43                        LOAD_ADDR_REG : In std_logic;
  44                        PCI_CLOCK : In std_logic;
  45                        PCI_RSTn : In std_logic;
  46                        ADDR_REG : Out std_logic_vector (31 downto 0) );
  47         end component;
  48
  49         component IO_REG
  50                 Port ( IO_DATA : In std_logic_vector (31 downto 0);
  51                        OE_PCI_AD : In std_logic;
  52                        PCI_CBEn : In std_logic_vector (3 downto 0);
  53                        PCI_CLOCK : In std_logic;
  54                        PCI_FRAMEn : In std_logic;
  55                        PCI_IDSEL : In std_logic;
  56                        PCI_IRDYn : In std_logic;
  57                        PCI_PAR : In std_logic;
  58                        PCI_RSTn : In std_logic;
  59                        AD_REG : Out std_logic_vector (31 downto 0);
  60                        CBE_REGn : Out std_logic_vector (3 downto 0);
  61                        FRAME_REGn : Out std_logic;
  62                        IDSEL_REG : Out std_logic;
  63                        IRDY_REGn : Out std_logic;
  64                        PAR_REG : Out std_logic;
  65                        PCI_AD : Out std_logic_vector (31 downto 0) );
  66         end component;
  67
  68         component IO_MUX
  69                 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
  70                        PCI_AD : In std_logic_vector (31 downto 0);
  71                        READ_SEL : In std_logic_vector (1 downto 0);
  72                        USER_DATA : In std_logic_vector (31 downto 0);
  73                        IO_DATA : Out std_logic_vector (31 downto 0) );
  74         end component;
  75
  76 begin
  77
  78         AD_REG <= AD_REG_DUMMY;
  79
  80         I5 : ADDRESS_REGISTER
  81         Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
  82                    LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
  83                    PCI_RSTn=>PCI_RSTn,
  84                    ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );
  85         I1 : IO_REG
  86         Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),
  87                    OE_PCI_AD=>READ_SEL(1),
  88                    PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
  89                    PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
  90                    PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
  91                    PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
  92                    AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
  93                    CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
  94                    FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
  95                    IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,
  96                    PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );
  97         I2 : IO_MUX
  98         Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),
  99         PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
 100         READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
 101         USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),
 102         IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );
 103
 104 end SCHEMATIC;