cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_00h.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONFIG_00H.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity CONFIG_00H is
  10         port
  11         (
  12                 VENDOR_ID :in std_logic_vector (15 downto 0);
  13                 CONF_DATA_00H :out std_logic_vector (31 downto 0)
  14         );
  15 end entity CONFIG_00H;
  16
  17 architecture CONFIG_00H_DESIGN of CONFIG_00H is
  18
  19  -- PCI Configuration Space Header Addr : HEX 00 --
  20
  21         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--????
  22         --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--????
  23
  24 begin
  25
  26         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
  27
  28 end architecture CONFIG_00H_DESIGN;