cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/interrupt.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: INTERRUPT.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all;
   8
   9 entity INTERRUPT is
  10         port
  11         (
  12                 PCI_CLOCK :in std_logic;
  13                 PCI_RSTn :in std_logic; -- PCI reset is asynchron (low active)
  14                 RESET :in std_logic;
  15                 TAST_SETn :in std_logic;
  16                 TAST_RESn :in std_logic;
  17                 INT_IN_0 :in std_logic;
  18                 INT_IN_1 :in std_logic;
  19                 INT_IN_2 :in std_logic;
  20                 INT_IN_3 :in std_logic;
  21                 INT_IN_4 :in std_logic;
  22                 INT_IN_5 :in std_logic;
  23                 INT_IN_6 :in std_logic;
  24                 INT_IN_7 :in std_logic;
  25                 TRDYn :in std_logic; -- event 1 after read of Interrupt status register (low active)
  26                 READ_XX5_4 :in std_logic; -- event 2 after read of Interrupt status register
  27                 INT_RES :in std_logic_vector(7 downto 0); -- clear selected interrupts
  28                 INT_MASKE :in std_logic_vector(7 downto 0); -- interrupt mask register
  29                 INT_REG :out std_logic_vector(7 downto 0); -- interrupt status register
  30                 INTAn :out std_logic; -- second interrupt line for PCI analyzer
  31                 PCI_INTAn :out std_logic -- PCI interrupt line
  32         );
  33
  34 end entity INTERRUPT;
  35
  36 architecture INTERRUPT_DESIGN of INTERRUPT is
  37
  38         signal SIG_TAST_Q :std_logic;
  39         signal SIG_TAST_Qn :std_logic;
  40
  41
  42         signal SIG_INTA :std_logic;
  43
  44         signal FF_A :std_logic_vector(7 downto 0);
  45         signal FF_B :std_logic_vector(7 downto 0);
  46         signal SET :std_logic_vector(7 downto 0);
  47
  48         signal SIG_PROPAGATE_INT :std_logic;
  49         signal SIG_PROPAGATE_INT_SECOND :std_logic;
  50         signal REG :std_logic_vector(7 downto 0);
  51
  52 begin
  53
  54
  55
  56
  57  ------------------------------------------------------
  58         process (PCI_CLOCK)
  59         begin
  60                 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
  61
  62  -- THIS IS BROKEN (it cycles the interrupt)
  63                         SIG_TAST_Q <= not (TAST_SETn and SIG_TAST_Qn);
  64                         SIG_TAST_Qn <= not (TAST_RESn and SIG_TAST_Q);
  65
  66                 end if;
  67         end process;
  68
  69  ------------------------------------------------------
  70
  71         process (PCI_CLOCK)
  72         begin
  73                 if (PCI_RSTn = '0') then
  74                         SET <= "00000000";
  75                         FF_A <= "00000000";
  76                         FF_B <= "00000000";
  77
  78                 elsif (rising_edge(PCI_CLOCK)) then
  79                         if (RESET = '1') then
  80                                 SET <= "00000000";
  81                                 FF_A <= "00000000";
  82                                 FF_B <= "00000000";
  83                         else
  84                                 FF_A(0) <= INT_IN_0; -- Receive FIFO Empty Flag
  85
  86                                 FF_A(1) <= INT_IN_1; -- Send FIFO Half Full
  87                                 FF_A(2) <= INT_IN_2;
  88                                 FF_A(3) <= INT_IN_3;
  89
  90                                 FF_A(4) <= INT_IN_4;
  91
  92                                 FF_A(5) <= INT_IN_5;
  93                                 FF_A(6) <= INT_IN_6;
  94                                 FF_A(7) <= INT_IN_7;
  95
  96                                 FF_B <= FF_A;
  97
  98                                 SET <= FF_A AND not FF_B;
  99                         end if;
 100                 end if;
 101         end process;
 102
 103         process (PCI_CLOCK,PCI_RSTn)
 104         begin
 105                 if (PCI_RSTn = '0') then
 106                         REG <= "00000000";
 107
 108                 elsif(rising_edge(PCI_CLOCK)) then
 109                         if(RESET = '1') then
 110                                 REG <= "00000000";
 111
 112                         -- elsif(SIG_TAST_Q = '1') then
 113                         -- REG <= "00000000" or SET;
 114
 115                         elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
 116                                 REG <= (REG AND NOT INT_RES) OR SET;
 117                         else
 118                                 REG <= REG OR SET;
 119                         end if;
 120                 end if;
 121         end process;
 122
 123         SIG_PROPAGATE_INT <= (not TAST_SETn)
 124         OR (REG(0) AND INT_MASKE(0))
 125         OR (REG(1) AND INT_MASKE(1))
 126         OR (REG(2) AND INT_MASKE(2))
 127         OR (REG(3) AND INT_MASKE(3))
 128         OR (REG(4) AND INT_MASKE(4))
 129         OR (REG(5) AND INT_MASKE(5))
 130         OR (REG(6) AND INT_MASKE(6))
 131         OR (REG(7) AND INT_MASKE(7));
 132
 133         process (PCI_CLOCK)
 134         begin
 135                 if(rising_edge(PCI_CLOCK)) then
 136                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
 137                 end if;
 138         end process;
 139
 140         INTAn <= not SIG_PROPAGATE_INT_SECOND;
 141         PCI_INTAn <= '0' when SIG_PROPAGATE_INT_SECOND = '0' else 'Z';
 142         INT_REG <= REG;
 143
 144 end architecture INTERRUPT_DESIGN;