cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/connecting_fsm.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONNECTING_FSM.VHD
   5
   6 library ieee ;
   7 use ieee.std_logic_1164.all ;
   8
   9 entity CONNECTING_FSM is
  10         port
  11         (
  12         PCI_CLOCK                               :in             std_logic;
  13         RESET                                           :in             std_logic;
  14         PSC_ENABLE                      :in             std_logic;
  15         SYNC_S_FIFO_EFn :in             std_logic;
  16         SPC_ENABLE                      :in             std_logic;
  17         SYNC_R_FIFO_FFn :in             std_logic;
  18         S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);
  19         S_FIFO_READn            :out    std_logic;
  20         R_FIFO_WRITEn           :out    std_logic;
  21         R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0)
  22         );
  23 end entity CONNECTING_FSM;
  24
  25 architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
  26
  27         signal REG                                              :std_logic_vector(7 downto 0);
  28         signal HELP_0,HELP_1    :std_logic;
  29         signal SIG_LOAD                         :std_logic;
  30
  31
  32 --**********************************************************
  33 --***         CONNECTING FSM CODIERUNG                   ***
  34 --**********************************************************
  35 --
  36 --
  37 --                                                 ---------- HELP_0
  38 --                                                       |--------- HELP_1
  39 --                                                       ||-------- LOAD
  40 --                                                 |||------- WRITE
  41 --                                                                                                                                                                                         ||||------ READ
  42 --                                                                                                                                                                                               |||||
  43         constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--
  44         constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ
  45         constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ
  46         constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD
  47         constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--
  48         constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE
  49         constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE
  50         constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE
  51
  52         signal STATES   :std_logic_vector(4 downto 0);
  53
  54 --************************************************************
  55 --***             FSM SPEICHER-AUTOMAT                     ***
  56 --************************************************************
  57
  58         attribute       syn_state_machine       :       boolean;
  59         attribute       syn_state_machine       of      STATES  :       signal  is      false;
  60
  61 --************************************************************
  62 --***                           REGISTER BESCHREIBUNG                  ***
  63 --************************************************************
  64
  65 begin
  66
  67         process (PCI_CLOCK)
  68         begin
  69                 if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
  70                         if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;
  71                                 elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;
  72                         end if;
  73                 end if;
  74         end process;
  75
  76 --************************************************************
  77 --***                           FSM BESCHREIBUNG                                 ***
  78 --************************************************************
  79
  80         process (PCI_CLOCK)
  81         begin
  82                 if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
  83
  84                         if      RESET   =       '1'     then    STATES <= S0;
  85                                 else
  86
  87                                         case    STATES is
  88
  89                                         when    S0      =>
  90                                                 if      PSC_ENABLE                      = '1'   and
  91                                                                 SPC_ENABLE                      =       '1'     and
  92                                                                 SYNC_S_FIFO_EFn =       '1'     then
  93
  94                                                                                                 STATES  <=      S1;
  95                                                         else
  96                                                                                                 STATES  <=      S0;
  97                                                 end if;
  98
  99                                         when    S1      =>      STATES  <=      S2;
 100                                         when    S2      =>      STATES  <=      S3;
 101                                         when    S3      =>      STATES  <=      S4;
 102
 103                                         when    S4      =>
 104                                                 if      SYNC_R_FIFO_FFn =       '1'     then
 105
 106                                                                                                 STATES  <=      S5;
 107                                                 else
 108                                 STATES  <=      S4;
 109                                                 end if;
 110
 111                                         when    S5      =>      STATES  <=      S6;
 112                                         when    S6      =>      STATES  <=      S7;
 113                                         when    S7      =>      STATES  <=      S0;
 114
 115                                         when others =>
 116
 117                                                                                                 STATES  <=      S0;
 118
 119                                 end case;               -- STATES
 120                         end if;                         -- RESET
 121                 end if;                                 -- PCI_CLOCK
 122         end process;                    -- PROCESS
 123
 124 --************************************************************
 125 --***           ZUWEISUNG       signal/out      <=      STATES             ***
 126 --************************************************************
 127
 128         HELP_0                          <=      STATES(4);
 129         HELP_1                          <=      STATES(3);
 130         SIG_LOAD                        <=      STATES(2);
 131         R_FIFO_WRITEn   <=      STATES(1);
 132         S_FIFO_READn    <=      STATES(0);
 133
 134         R_FIFO_D_IN             <=      REG;
 135
 136 end architecture CONNECTING_FSM_DESIGN;