cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_sync_module.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name "sync_module.v"                                   ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Tadej Markovic, tadej@opencores.org                   ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the README.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 ////                                                              ////
  17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
  18 ////                                                              ////
  19 //// This source file may be used and distributed without         ////
  20 //// restriction provided that this copyright statement is not    ////
  21 //// removed from the file and that any derivative work contains  ////
  22 //// the original copyright notice and the associated disclaimer. ////
  23 ////                                                              ////
  24 //// This source file is free software; you can redistribute it   ////
  25 //// and/or modify it under the terms of the GNU Lesser General   ////
  26 //// Public License as published by the Free Software Foundation; ////
  27 //// either version 2.1 of the License, or (at your option) any   ////
  28 //// later version.                                               ////
  29 ////                                                              ////
  30 //// This source is distributed in the hope that it will be       ////
  31 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  33 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  34 //// details.                                                     ////
  35 ////                                                              ////
  36 //// You should have received a copy of the GNU Lesser General    ////
  37 //// Public License along with this source; if not, download it   ////
  38 //// from http://www.opencores.org/lgpl.shtml                     ////
  39 ////                                                              ////
  40 //////////////////////////////////////////////////////////////////////
  41 //
  42 // CVS Revision History
  43 //
  44 // $Log: pci_sync_module.v,v $
  45 // Revision 1.1  2007-03-20 17:50:56  sithglan
  46 // add shit
  47 //
  48 // Revision 1.3  2003/08/14 13:06:03  simons
  49 // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  50 //
  51 // Revision 1.2  2003/03/26 13:16:18  mihad
  52 // Added the reset value parameter to the synchronizer flop module.
  53 // Added resets to all synchronizer flop instances.
  54 // Repaired initial sync value in fifos.
  55 //
  56 // Revision 1.1  2003/01/27 16:49:31  mihad
  57 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  58 //
  59 // Revision 1.1  2002/02/01 14:43:31  mihad
  60 // *** empty log message ***
  61 //
  62 //
  63 //
  64
  65 // synopsys translate_off
  66 `include "timescale.v"
  67 // synopsys translate_on
  68
  69 module pci_sync_module
  70 (
  71                                         set_clk_in,
  72                                         delete_clk_in,
  73                                         reset_in,
  74                                         delete_set_out,
  75                                         block_set_out,
  76                                         delete_in
  77 );
  78
  79 // system inputs from two clock domains
  80 input   set_clk_in;
  81 input   delete_clk_in;
  82 input   reset_in;
  83 // control outputs
  84 output  delete_set_out;
  85 output  block_set_out;
  86 // control input
  87 input   delete_in;
  88
  89 // internal signals
  90 reg             del_bit;
  91 wire    meta_del_bit;
  92 reg             sync_del_bit;
  93 reg             delayed_del_bit;
  94 wire    meta_bckp_bit;
  95 reg             sync_bckp_bit;
  96 reg             delayed_bckp_bit;
  97
  98
  99 // DELETE_IN input FF - when set must be active, until it is sinchronously cleared
 100 always@(posedge delete_clk_in or posedge reset_in)
 101 begin
 102         if (reset_in)
 103                 del_bit <= 1'b0;
 104         else
 105         begin
 106                 if (!delayed_bckp_bit && sync_bckp_bit)
 107                         del_bit <= 1'b0;
 108                 else if (delete_in)
 109                         del_bit <= 1'b1;
 110         end
 111 end
 112 assign  block_set_out = del_bit;
 113
 114 // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
 115 pci_synchronizer_flop   #(1, 0) delete_sync
 116 (
 117     .data_in        (del_bit),
 118     .clk_out        (set_clk_in),
 119     .sync_data_out  (meta_del_bit),
 120     .async_reset    (reset_in)
 121 ) ;
 122
 123 // Final synchronization of del_bit signal to the set clock domain
 124 always@(posedge set_clk_in or posedge reset_in)
 125 begin
 126         if (reset_in)
 127                 sync_del_bit <= 1'b0;
 128         else
 129                 sync_del_bit <= meta_del_bit;
 130 end
 131
 132 // Delayed sync_del_bit signal for one clock period pulse generation
 133 always@(posedge set_clk_in or posedge reset_in)
 134 begin
 135         if (reset_in)
 136                 delayed_del_bit <= 1'b0;
 137         else
 138                 delayed_del_bit <= sync_del_bit;
 139 end
 140
 141 assign  delete_set_out = !delayed_del_bit && sync_del_bit;
 142
 143 // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
 144 pci_synchronizer_flop   #(1, 0) clear_delete_sync
 145 (
 146     .data_in        (sync_del_bit),
 147     .clk_out        (delete_clk_in),
 148     .sync_data_out  (meta_bckp_bit),
 149     .async_reset    (reset_in)
 150 ) ;
 151
 152 // Final synchronization of sync_del_bit signal to the delete clock domain
 153 always@(posedge delete_clk_in or posedge reset_in)
 154 begin
 155         if (reset_in)
 156                 sync_bckp_bit <= 1'b0;
 157         else
 158                 sync_bckp_bit <= meta_bckp_bit;
 159 end
 160
 161 // Delayed sync_bckp_bit signal for one clock period pulse generation
 162 always@(posedge delete_clk_in or posedge reset_in)
 163 begin
 164         if (reset_in)
 165                 delayed_bckp_bit <= 1'b0;
 166         else
 167                 delayed_bckp_bit <= sync_bckp_bit;
 168 end
 169
 170 endmodule