cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/heartbeat.vhd

   1 library ieee;
   2
   3 use ieee.std_logic_1164.all;
   4 use ieee.std_logic_unsigned.all;
   5
   6 entity heartbeat is
   7 generic (
   8         divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
   9 );
  10
  11 port (
  12         clk_i : in std_logic;
  13         nrst_i : in std_logic;
  14         led2_o : out std_logic;
  15         led3_o : out std_logic;
  16         led4_o : out std_logic;
  17         led5_o : out std_logic
  18 );
  19
  20 end heartbeat;
  21
  22 architecture rtl of heartbeat is
  23 begin
  24
  25 process(clk_i, nrst_i)
  26 variable counter : std_logic_vector(31 downto 0);
  27 variable state : std_logic_vector(3 downto 0) := "0001";
  28 variable direction : std_logic := '0';
  29 begin
  30
  31 if (clk_i'event AND clk_i = '1') then
  32         if nrst_i = '0' then
  33                 counter := (others => '0');
  34         else
  35                 led2_o <= state(0);
  36                 led3_o <= state(1);
  37                 led4_o <= state(2);
  38                 led5_o <= state(3);
  39                 counter := counter + 1;
  40                 if counter = divider then
  41                         if state(3) = '1' then
  42                                 direction := '1';
  43                         end if;
  44
  45                         if state(0) = '1' then
  46                                 direction := '0';
  47                         end if;
  48
  49                         if direction = '0' then
  50                                 state(3 downto 1) := state(2 downto 0);
  51                                 state(0) := '0';
  52                         else
  53                                 state(2 downto 0) := state(3 downto 1);
  54                                 state(3) := '0';
  55                         end if;
  56                         counter := (others => '0');
  57                 end if;
  58         end if;
  59 end if;
  60 end process;
  61 end architecture;