cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/connecting_fsm.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONNECTING_FSM.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all;
   8
   9 entity CONNECTING_FSM is
  10         port
  11         (
  12                 PCI_CLOCK :in std_logic;
  13                 RESET :in std_logic;
  14                 PSC_ENABLE :in std_logic;
  15                 SYNC_S_FIFO_EFn :in std_logic;
  16                 SPC_ENABLE :in std_logic;
  17                 SYNC_R_FIFO_FFn :in std_logic;
  18                 S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);
  19                 S_FIFO_READn :out std_logic;
  20                 R_FIFO_WRITEn :out std_logic;
  21                 R_FIFO_D_IN :out std_logic_vector(7 downto 0)
  22         );
  23 end entity CONNECTING_FSM;
  24
  25 architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
  26
  27         signal REG :std_logic_vector(7 downto 0);
  28         signal HELP_0,HELP_1 :std_logic;
  29         signal SIG_LOAD :std_logic;
  30
  31
  32  --**********************************************************
  33  --*** CONNECTING FSM CODIERUNG ***
  34  --**********************************************************
  35  --
  36  --
  37  -- ---------- HELP_0
  38  -- |--------- HELP_1
  39  -- ||-------- LOAD
  40  -- |||------- WRITE
  41  -- ||||------ READ
  42  -- |||||
  43         constant S0 :std_logic_vector(4 downto 0) := "00011";--
  44         constant S1 :std_logic_vector(4 downto 0) := "01010";--READ
  45         constant S2 :std_logic_vector(4 downto 0) := "10010";--READ
  46         constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD
  47         constant S4 :std_logic_vector(4 downto 0) := "11011";--
  48         constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE
  49         constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE
  50         constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE
  51
  52         signal STATES :std_logic_vector(4 downto 0);
  53
  54  --************************************************************
  55  --*** FSM SPEICHER-AUTOMAT ***
  56  --************************************************************
  57
  58         attribute syn_state_machine : boolean;
  59         attribute syn_state_machine of STATES : signal is false;
  60
  61 --************************************************************
  62 --*** REGISTER BESCHREIBUNG ***
  63 --************************************************************
  64
  65 begin
  66
  67         process (PCI_CLOCK)
  68         begin
  69                 if (rising_edge(PCI_CLOCK)) then
  70                         if SIG_LOAD = '1' then
  71                                 REG <= S_FIFO_Q_OUT;
  72
  73                         elsif SIG_LOAD = '0' then
  74                                 REG <= REG;
  75                         end if;
  76                 end if;
  77  end process;
  78
  79  --************************************************************
  80  --*** FSM BESCHREIBUNG ***
  81  --************************************************************
  82
  83 process (PCI_CLOCK)
  84 begin
  85         if (rising_edge(PCI_CLOCK)) then
  86
  87                 if RESET = '1' then
  88                         STATES <= S0;
  89                 else
  90
  91                        case STATES is
  92
  93                        when S0 =>
  94                                if PSC_ENABLE = '1' and SPC_ENABLE = '1' and SYNC_S_FIFO_EFn = '1' then
  95                                        STATES <= S1;
  96                                else
  97                                        STATES <= S0;
  98                                end if;
  99
 100                        when S1 =>
 101                                STATES <= S2;
 102
 103                        when S2 =>
 104                                STATES <= S3;
 105
 106                        when S3 =>
 107                                STATES <= S4;
 108
 109                        when S4 =>
 110                                if SYNC_R_FIFO_FFn = '1' then
 111                                        STATES <= S5;
 112                                else
 113                                        STATES <= S4;
 114                                end if;
 115
 116                        when S5 =>
 117                                STATES <= S6;
 118
 119                        when S6 =>
 120                                STATES <= S7;
 121
 122                        when S7 =>
 123                                STATES <= S0;
 124
 125                        when others =>
 126                                STATES <= S0;
 127
 128                         end case; -- STATES
 129                 end if; -- RESET
 130         end if; -- PCI_CLOCK
 131 end process; -- PROCESS
 132
 133  --************************************************************
 134  --*** ZUWEISUNG signal/out <= STATES ***
 135  --************************************************************
 136
 137 HELP_0 <= STATES(4);
 138 HELP_1 <= STATES(3);
 139 SIG_LOAD <= STATES(2);
 140 R_FIFO_WRITEn <= STATES(1);
 141 S_FIFO_READn <= STATES(0);
 142
 143 R_FIFO_D_IN <= REG;
 144
 145 end architecture CONNECTING_FSM_DESIGN;