cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/fifo_control.vhd

   1 -- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
   2
   3
   4 LIBRARY ieee;
   5
   6 USE ieee.std_logic_1164.ALL;
   7 USE ieee.numeric_std.ALL;
   8
   9
  10 entity FIFO_CONTROL is
  11         Port ( FIFO_RDn : In std_logic;
  12                FLAG_IN_0 : In std_logic;
  13                FLAG_IN_4 : In std_logic;
  14                HOLD : In std_logic;
  15                KONST_1 : In std_logic;
  16                PCI_CLOCK : In std_logic;
  17                PSC_ENABLE : In std_logic;
  18                R_EFn : In std_logic;
  19                R_FFn : In std_logic;
  20                R_HFn : In std_logic;
  21                RESET : In std_logic;
  22                S_EFn : In std_logic;
  23                S_FFn : In std_logic;
  24                S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
  25                S_HFn : In std_logic;
  26                SERIAL_IN : In std_logic;
  27                SPC_ENABLE : In std_logic;
  28                SPC_RDY_IN : In std_logic;
  29                WRITE_XX1_0 : In std_logic;
  30                R_ERROR : Out std_logic;
  31                R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
  32                R_FIFO_READn : Out std_logic;
  33                R_FIFO_RESETn : Out std_logic;
  34                R_FIFO_RETRANSMITn : Out std_logic;
  35                R_FIFO_WRITEn : Out std_logic;
  36                RESERVE : Out std_logic;
  37                S_ERROR : Out std_logic;
  38                S_FIFO_READn : Out std_logic;
  39                S_FIFO_RESETn : Out std_logic;
  40                S_FIFO_RETRANSMITn : Out std_logic;
  41                S_FIFO_WRITEn : Out std_logic;
  42                SERIAL_OUT : Out std_logic;
  43                SPC_RDY_OUT : Out std_logic;
  44                SR_ERROR : Out std_logic;
  45                SYNC_FLAG : Out std_logic_vector (7 downto 0));
  46 end FIFO_CONTROL;
  47
  48 architecture SCHEMATIC of FIFO_CONTROL is
  49
  50         SIGNAL gnd : std_logic := '0';
  51         SIGNAL vcc : std_logic := '1';
  52
  53         signal XXXR_FIFO_WRITEn : std_logic;
  54         signal XXXS_FIFO_READn : std_logic;
  55         signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
  56         signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
  57
  58         component SER_PAR_CON
  59                 Port ( PCI_CLOCK : In std_logic;
  60                        RESET : In std_logic;
  61                        SERIAL_IN : In std_logic;
  62                        SPC_ENABLE : In std_logic;
  63                        SYNC_R_FIFO_FFn : In std_logic;
  64                        PAR_OUT : Out std_logic_vector (7 downto 0);
  65                        R_FIFO_WRITEn : Out std_logic;
  66                        SPC_RDY_OUT : Out std_logic );
  67         end component;
  68
  69         component PAR_SER_CON
  70                 Port ( PAR_IN : In std_logic_vector (7 downto 0);
  71                        PCI_CLOCK : In std_logic;
  72                        PSC_ENABLE : In std_logic;
  73                        RESET : In std_logic;
  74                        SPC_RDY_IN : In std_logic;
  75                        SYNC_S_FIFO_EFn : In std_logic;
  76                        S_FIFO_READn : Out std_logic;
  77                        SER_OUT : Out std_logic );
  78         end component;
  79
  80         component FIFO_IO_CONTROL
  81                 Port ( FIFO_RDn : In std_logic;
  82                        PCI_CLOCK : In std_logic;
  83                        RESET : In std_logic;
  84                        SYNC_FLAG_1 : In std_logic;
  85                        SYNC_FLAG_7 : In std_logic;
  86                        WRITE_XX1_0 : In std_logic;
  87                        R_ERROR : Out std_logic;
  88                        R_FIFO_READn : Out std_logic;
  89                        R_FIFO_RESETn : Out std_logic;
  90                        R_FIFO_RETRANSMITn : Out std_logic;
  91                        S_ERROR : Out std_logic;
  92                        S_FIFO_RESETn : Out std_logic;
  93                        S_FIFO_RETRANSMITn : Out std_logic;
  94                        S_FIFO_WRITEn : Out std_logic;
  95                        SR_ERROR : Out std_logic );
  96         end component;
  97
  98         component CONNECTING_FSM
  99                 Port ( PCI_CLOCK : In std_logic;
 100                        PSC_ENABLE : In std_logic;
 101                        RESET : In std_logic;
 102                        S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
 103                        SPC_ENABLE : In std_logic;
 104                        SYNC_R_FIFO_FFn : In std_logic;
 105                        SYNC_S_FIFO_EFn : In std_logic;
 106                        R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
 107                        R_FIFO_WRITEn : Out std_logic;
 108                        S_FIFO_READn : Out std_logic );
 109         end component;
 110
 111         component FLAG_BUS
 112                 Port ( FLAG_IN_0 : In std_logic;
 113                        FLAG_IN_4 : In std_logic;
 114                        HOLD : In std_logic;
 115                        KONS_1 : In std_logic;
 116                        PCI_CLOCK : In std_logic;
 117                        R_EFn : In std_logic;
 118                        R_FFn : In std_logic;
 119                        R_HFn : In std_logic;
 120                        S_EFn : In std_logic;
 121                        S_FFn : In std_logic;
 122                        S_HFn : In std_logic;
 123                        SYNC_FLAG : Out std_logic_vector (7 downto 0) );
 124         end component;
 125
 126 begin
 127
 128         SYNC_FLAG <= SYNC_FLAG_DUMMY;
 129
 130         RESERVE <= gnd;
 131         I23 : SER_PAR_CON
 132         Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
 133                    SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
 134                    SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
 135                    PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
 136                    R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
 137         I22 : PAR_SER_CON
 138         Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 139                    PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
 140                    RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
 141                    SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
 142                    S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
 143         I21 : FIFO_IO_CONTROL
 144         Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
 145                    SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
 146                    SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
 147                    WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
 148                    R_FIFO_READn=>R_FIFO_READn,
 149                    R_FIFO_RESETn=>R_FIFO_RESETn,
 150                    R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
 151                    S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
 152                    S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
 153                    S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
 154         I20 : CONNECTING_FSM
 155         Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
 156                    RESET=>RESET,
 157                    S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 158                    SPC_ENABLE=>SPC_ENABLE,
 159                    SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
 160                    SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
 161                    R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
 162                    R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
 163                    S_FIFO_READn=>XXXS_FIFO_READn );
 164         I19 : FLAG_BUS
 165         Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
 166                    KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
 167                    R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
 168                    S_HFn=>S_HFn,
 169                    SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
 170
 171 end SCHEMATIC;