MCOLL_PAD_I : IN std_logic;
MCRS_PAD_I : IN std_logic;
MD_PAD_IO : INOUT std_logic;
- MDC_PAD_O : OUT std_logic
+ MDC_PAD_O : OUT std_logic;
+
+ LED_2 : OUT std_logic
);
end ethernet;
mdc_pad_o : OUT std_logic;
md_pad_o : OUT std_logic;
md_padoe_o : OUT std_logic;
+ m_wb_cti_o : OUT std_logic_vector(2 downto 0);
+ m_wb_bte_o : OUT std_logic_vector(1 downto 0);
int_o : OUT std_logic
);
END COMPONENT;
);
END COMPONENT;
+COMPONENT eth_cop
+PORT(
+ wb_clk_i : IN std_logic;
+ wb_rst_i : IN std_logic;
+ m1_wb_adr_i : IN std_logic_vector(31 downto 0);
+ m1_wb_sel_i : IN std_logic_vector(3 downto 0);
+ m1_wb_we_i : IN std_logic;
+ m1_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m1_wb_cyc_i : IN std_logic;
+ m1_wb_stb_i : IN std_logic;
+ m2_wb_adr_i : IN std_logic_vector(31 downto 0);
+ m2_wb_sel_i : IN std_logic_vector(3 downto 0);
+ m2_wb_we_i : IN std_logic;
+ m2_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m2_wb_cyc_i : IN std_logic;
+ m2_wb_stb_i : IN std_logic;
+ s1_wb_ack_i : IN std_logic;
+ s1_wb_err_i : IN std_logic;
+ s1_wb_dat_i : IN std_logic_vector(31 downto 0);
+ s2_wb_ack_i : IN std_logic;
+ s2_wb_err_i : IN std_logic;
+ s2_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ m1_wb_ack_o : OUT std_logic;
+ m1_wb_err_o : OUT std_logic;
+ m2_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ m2_wb_ack_o : OUT std_logic;
+ m2_wb_err_o : OUT std_logic;
+ s1_wb_adr_o : OUT std_logic_vector(31 downto 0);
+ s1_wb_sel_o : OUT std_logic_vector(3 downto 0);
+ s1_wb_we_o : OUT std_logic;
+ s1_wb_cyc_o : OUT std_logic;
+ s1_wb_stb_o : OUT std_logic;
+ s1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ s2_wb_adr_o : OUT std_logic_vector(31 downto 0);
+ s2_wb_sel_o : OUT std_logic_vector(3 downto 0);
+ s2_wb_we_o : OUT std_logic;
+ s2_wb_cyc_o : OUT std_logic;
+ s2_wb_stb_o : OUT std_logic;
+ s2_wb_dat_o : OUT std_logic_vector(31 downto 0)
+ );
+END COMPONENT;
+
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);
+signal m_wb_cti_o : std_logic_vector(2 downto 0);
+signal m_wb_bte_o : std_logic_vector(1 downto 0);
+
BEGIN
PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
wb_adr_i <= wbm_adr_o (11 downto 2);
+wb_clk_i <= PCI_CLOCK;
+
Inst_pci_bridge32: pci_bridge32 PORT MAP(
wb_clk_i => wb_clk_i ,
wb_rst_i => '0',
wbs_cyc_i => m_wb_cyc_o,
wbs_stb_i => m_wb_stb_o,
wbs_we_i => m_wb_we_o,
- wbs_cti_i => (others => '0'),
- wbs_bte_i => (others => '0'),
+ wbs_cti_i => m_wb_cti_o,
+ wbs_bte_i => m_wb_bte_o,
wbs_ack_o => m_wb_ack_i,
-- wbs_rty_o => ,
wbs_err_o => m_wb_err_i,
mtx_clk_pad_i => MTX_CLK_PAD_I,
mtxd_pad_o => MTXD_PAD_O,
mtxen_pad_o => MTXEN_PAD_O,
- -- mtxerr_pad_o => ,
+ mtxerr_pad_o => LED_2,
mrx_clk_pad_i => MRX_CLK_PAD_I,
mrxd_pad_i => MRXD_PAD_I,
mrxdv_pad_i => MRXDV_PAD_I,
md_pad_i => MD_PAD_IO,
md_pad_o => md_pad_o,
md_padoe_o => md_padoe_o,
+ m_wb_cti_o => m_wb_cti_o,
+ m_wb_bte_o => m_wb_bte_o,
int_o => int_o
);
+--Inst_eth_cop: eth_cop PORT MAP(
+-- wb_clk_i => ,
+-- wb_rst_i => ,
+-- m1_wb_adr_i => ,
+-- m1_wb_sel_i => ,
+-- m1_wb_we_i => ,
+-- m1_wb_dat_o => ,
+-- m1_wb_dat_i => ,
+-- m1_wb_cyc_i => ,
+-- m1_wb_stb_i => ,
+-- m1_wb_ack_o => ,
+-- m1_wb_err_o => ,
+-- m2_wb_adr_i => ,
+-- m2_wb_sel_i => ,
+-- m2_wb_we_i => ,
+-- m2_wb_dat_o => ,
+-- m2_wb_dat_i => ,
+-- m2_wb_cyc_i => ,
+-- m2_wb_stb_i => ,
+-- m2_wb_ack_o => ,
+-- m2_wb_err_o => ,
+-- s1_wb_adr_o => ,
+-- s1_wb_sel_o => ,
+-- s1_wb_we_o => ,
+-- s1_wb_cyc_o => ,
+-- s1_wb_stb_o => ,
+-- s1_wb_ack_i => ,
+-- s1_wb_err_i => ,
+-- s1_wb_dat_i => ,
+-- s1_wb_dat_o => ,
+-- s2_wb_adr_o => ,
+-- s2_wb_sel_o => ,
+-- s2_wb_we_o => ,
+-- s2_wb_cyc_o => ,
+-- s2_wb_stb_o => ,
+-- s2_wb_ack_i => ,
+-- s2_wb_err_i => ,
+-- s2_wb_dat_i => ,
+-- s2_wb_dat_o =>
+--);
+
end architecture ethernet_arch;