clock

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index d181c526bad9c216cbb6ff03020f51cd437daf32..184e744cddbf5d683298c32917e9cfe585fbd154 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -277,6 +277,8 @@ end generate;
 
 wb_adr_i <= wbm_adr_o (11 downto 2);
 
+wb_clk_i <= PCI_CLOCK;
+
 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
         wb_rst_i => '0',