use ieee.std_logic_1164.all;
entity IO_REG is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- PCI_FRAMEn :in std_logic;
- PCI_IRDYn :in std_logic;
- PCI_IDSEL :in std_logic;
- PCI_PAR :in std_logic;
- PCI_CBEn :in std_logic_vector ( 3 downto 0);
- OE_PCI_AD :in std_logic;
- IO_DATA :in std_logic_vector (31 downto 0);
- AD_REG :out std_logic_vector (31 downto 0);
- CBE_REGn :out std_logic_vector ( 3 downto 0);
- FRAME_REGn :out std_logic;
- IRDY_REGn :out std_logic;
- IDSEL_REG :out std_logic;
- PAR_REG :out std_logic;
- PCI_AD :out std_logic_vector (31 downto 0) -- t/s
- );
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ PCI_FRAMEn :in std_logic;
+ PCI_IRDYn :in std_logic;
+ PCI_IDSEL :in std_logic;
+ PCI_PAR :in std_logic;
+ PCI_CBEn :in std_logic_vector ( 3 downto 0);
+ OE_PCI_AD :in std_logic;
+ IO_DATA :in std_logic_vector (31 downto 0);
+ AD_REG :out std_logic_vector (31 downto 0);
+ CBE_REGn :out std_logic_vector ( 3 downto 0);
+ FRAME_REGn :out std_logic;
+ IRDY_REGn :out std_logic;
+ IDSEL_REG :out std_logic;
+ PAR_REG :out std_logic;
+ PCI_AD :out std_logic_vector (31 downto 0) -- t/s
+ );
end entity IO_REG;
architecture IO_REG_DESIGN of IO_REG is
- signal REG_AD :std_logic_vector (31 downto 0);
- signal REG_CBEn :std_logic_vector ( 3 downto 0);
- signal REG_FRAMEn :std_logic;
- signal REG_IRDYn :std_logic;
- signal REG_IDSEL :std_logic;
- signal REG_PAR :std_logic;
+ signal REG_AD :std_logic_vector (31 downto 0);
+ signal REG_CBEn :std_logic_vector ( 3 downto 0);
+ signal REG_FRAMEn :std_logic;
+ signal REG_IRDYn :std_logic;
+ signal REG_IDSEL :std_logic;
+ signal REG_PAR :std_logic;
-begin
+begin
- process (PCI_CLOCK, PCI_RSTn)
- begin
- if PCI_RSTn = '0' then
+ process (PCI_CLOCK, PCI_RSTn)
+ begin
+ if PCI_RSTn = '0' then
+ REG_AD <= X"00000000";
+ REG_CBEn <= "0000";
+ REG_FRAMEn <= '1';
+ REG_IRDYn <= '1';
+ REG_IDSEL <= '0';
+ REG_PAR <= '0';
- REG_AD <= X"00000000";
- REG_CBEn <= "0000";
- REG_FRAMEn <= '1';
- REG_IRDYn <= '1';
- REG_IDSEL <= '0';
- REG_PAR <= '0';
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ REG_AD <= IO_DATA;
+ REG_CBEn <= PCI_CBEn;
+ REG_FRAMEn <= PCI_FRAMEn;
+ REG_IRDYn <= PCI_IRDYn;
+ REG_IDSEL <= PCI_IDSEL;
+ REG_PAR <= PCI_PAR;
+ end if;
+ end process;
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
- REG_AD <= IO_DATA;
- REG_CBEn <= PCI_CBEn;
- REG_FRAMEn <= PCI_FRAMEn;
- REG_IRDYn <= PCI_IRDYn;
- REG_IDSEL <= PCI_IDSEL;
- REG_PAR <= PCI_PAR;
-
- end if;
- end process;
-
- PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
-
- AD_REG <= REG_AD;
- CBE_REGn <= REG_CBEn;
- FRAME_REGn <= REG_FRAMEn;
- IRDY_REGn <= REG_IRDYn;
- IDSEL_REG <= REG_IDSEL;
- PAR_REG <= REG_PAR;
+ AD_REG <= REG_AD;
+ CBE_REGn <= REG_CBEn;
+ FRAME_REGn <= REG_FRAMEn;
+ IRDY_REGn <= REG_IRDYn;
+ IDSEL_REG <= REG_IDSEL;
+ PAR_REG <= REG_PAR;
end architecture IO_REG_DESIGN;