verilog work "source/sync.v"
-verilog work "source/disp_dec.v"
-verilog work "source/wb_7seg.v"
verilog work "source/pcidec.v"
verilog work "source/pcidmux.v"
vhdl work "source/new_pciregs.vhd"
vhdl work "source/pcipargen.vhd"
vhdl work "source/new_pci32tlite.vhd"
-vhdl work "source/vga_main.vhd"
-vhdl work "source/top_pci_7seg.vhd"
+vhdl work "source/top_raggedstone.vhd"
+vhdl work "source/heartbeat.vhd"