level

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index a79c47032468b8b59def86cd4406abdbf882ad5f..4becb68de5b660595716589d730a2a40835bba91 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -91,6 +91,9 @@ architecture SCHEMATIC of dhwk is
    signal SERIAL_OUT : std_logic;\r
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
+   signal control0       : std_logic_vector(35 downto 0);\r
+   signal data       : std_logic_vector(35 downto 0);\r
+   signal trig0      : std_logic_vector(7 downto 0);\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
@@ -221,6 +224,24 @@ component fifo_generator_v3_2
         prog_full: OUT std_logic);\r
 end component;\r
 \r
+component icon\r
+port\r
+       (\r
+        control0    :   out std_logic_vector(35 downto 0)\r
+       );\r
+end component;\r
+\r
+  component ila\r
+    port\r
+    (\r
+      control     : in    std_logic_vector(35 downto 0);\r
+      clk         : in    std_logic;\r
+      data        : in    std_logic_vector(35 downto 0);\r
+      trig0       : in    std_logic_vector(7 downto 0)\r
+    );\r
+  end component;\r
+\r
+\r
 begin\r
        SERIAL_IN <= SERIAL_OUT;\r
        SPC_RDY_IN <= SPC_RDY_OUT;\r
@@ -229,6 +250,29 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
+       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+       data(0) <= watch;\r
+       \r
+       data(1) <= R_EFn;\r
+       data(2) <= R_HFn;\r
+       data(3) <= R_FFn;\r
+       data(4) <= R_FIFO_READn;\r
+       data(5) <= R_FIFO_RESETn;\r
+       data(6) <= R_FIFO_RTn;\r
+       data(7) <= R_FIFO_WRITEn;\r
+       data(8) <= S_EFn;\r
+       data(9) <= S_HFn;\r
+       data(10) <= S_FFn;\r
+       data(11) <= S_FIFO_READn;\r
+       data(12) <= S_FIFO_RESETn;\r
+       data(13) <= S_FIFO_RTn;\r
+       data(14) <= S_FIFO_WRITEn;\r
+       data(15) <= SERIAL_IN;\r
+       data(16) <= SPC_RDY_IN;\r
+       data(17) <= SERIAL_OUT;\r
+       data(18) <= SPC_RDY_OUT;\r
+       data(26 downto 19) <= S_FIFO_Q_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -321,4 +365,19 @@ send_fifo : fifo_generator_v3_2
                         empty => S_EFn,\r
                         full => S_FFn,\r
                         prog_full => S_HFn);\r
+\r
+  i_icon : icon\r
+      port map\r
+          (\r
+               control0    => control0\r
+         );\r
+\r
+  i_ila : ila\r
+    port map\r
+    (\r
+      control   => control0,\r
+      clk       => PCI_CLOCK,\r
+      data      => data,\r
+      trig0     => trig0\r
+    );\r
 end SCHEMATIC;\r