---+-------------------------------------------------------------------------------------------------+\r
---| |\r
---| File: top.vhd |\r
---| |\r
---| Components: pci32lite.vhd |\r
---| pciwbsequ.vhd |\r
---| pcidmux.vhd |\r
---| pciregs.vhd |\r
---| pcipargen.vhd |\r
---| -- Libs -- |\r
---| ona.vhd |\r
---| |\r
---| Description: RS1 PCI Demo : (TOP) Main file. |\r
---| |\r
---| |\r
---| |\r
---+-------------------------------------------------------------------------------------------------+\r
---| |\r
---| Revision history : |\r
---| Date Version Author Description |\r
---| |\r
---| |\r
---| To do: |\r
---| |\r
---+-------------------------------------------------------------------------------------------------+\r
-\r
-\r
---+-----------------------------------------------------------------------------+\r
---| LIBRARIES |\r
---+-----------------------------------------------------------------------------+\r
-\r
library ieee;\r
use ieee.std_logic_1164.all;\r
use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
---+-----------------------------------------------------------------------------+\r
---| ENTITY |\r
---+-----------------------------------------------------------------------------+\r
-\r
entity dhwk is\r
port (\r
\r
end dhwk;\r
\r
\r
---+-----------------------------------------------------------------------------+\r
---| ARCHITECTURE |\r
---+-----------------------------------------------------------------------------+\r
-\r
architecture dhwk_arch of dhwk is\r
\r
\r
---+-----------------------------------------------------------------------------+\r
---| COMPONENTS |\r
---+-----------------------------------------------------------------------------+\r
-\r
component pci32tlite\r
port (\r
\r
);\r
end component;\r
\r
+component generic_fifo_sc_a\r
+port (\r
+ clk : in std_logic;\r
+ rst : in std_logic;\r
+ clr : in std_logic;\r
+ din : in std_logic_vector(7 downto 0);\r
+ we : in std_logic;\r
+ dout : out std_logic_vector(7 downto 0);\r
+ re : in std_logic;\r
+ full : out std_logic;\r
+ full_r : out std_logic;\r
+ empty : out std_logic;\r
+ empty_r : out std_logic;\r
+ full_n : out std_logic;\r
+ full_n_r : out std_logic;\r
+ empty_n : out std_logic;\r
+ empty_n_r : out std_logic;\r
+ level : out std_logic_vector(1 downto 0)\r
+);\r
+end component;\r
+\r
+component generic_dpram\r
+port (\r
+ rclk : in std_logic;\r
+ rrst : in std_logic;\r
+ rce : in std_logic;\r
+ oe : in std_logic;\r
+ raddr : in std_logic_vector(11 downto 0);\r
+ do : out std_logic_vector(7 downto 0);\r
+ wclk : in std_logic;\r
+ wrst : in std_logic;\r
+ wce : in std_logic;\r
+ we : in std_logic;\r
+ waddr : in std_logic_vector(11 downto 0);\r
+ di : in std_logic_vector(7 downto 0)\r
+);\r
+end component;\r
\r
---+-----------------------------------------------------------------------------+\r
---| CONSTANTS |\r
---+-----------------------------------------------------------------------------+\r
---+-----------------------------------------------------------------------------+\r
---| SIGNALS |\r
---+-----------------------------------------------------------------------------+\r
\r
signal wb_adr : std_logic_vector(24 downto 1); \r
signal wb_dat_out : std_logic_vector(15 downto 0);\r
\r
begin\r
\r
---+-----------------------------------------+\r
---| PCI Target |\r
---+-----------------------------------------+\r
-\r
u_pci: component pci32tlite\r
port map(\r
clk33 => PCI_CLK,\r
-- debug_access => LED2\r
);\r
\r
---+-----------------------------------------+\r
---| WB-7seg |\r
---+-----------------------------------------+\r
-\r
my_heartbeat: component heartbeat\r
port map( \r
clk_i => PCI_CLK,\r