+= heartbeat

diff --git a/heartbeat/Makefile b/heartbeat/Makefile
index b0ba87c1c193ada3b5be37ac1e74e43f4ff9ce0c..0399ea3d0dc70db5e75976d5d4e76da5440e7b90 100644 (file)
--- a/heartbeat/Makefile
+++ b/heartbeat/Makefile
@@ -19,7 +19,7 @@ ngdbuild: $(PROJECT).ngc $(PROJECT).ngd
 $(PROJECT).ngc:
        @# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1
        echo work > $(PROJECT).lso
 $(PROJECT).ngc:
        @# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1
        echo work > $(PROJECT).lso

-       xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr &> tmp/build.xst.log
+       xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr

        #cat $(PROJECT).syr
        mv $(PROJECT).syr $(TMP)
        mv $(PROJECT).ngr $(PROJECT).lso $(TMP)
        #cat $(PROJECT).syr
        mv $(PROJECT).syr $(TMP)
        mv $(PROJECT).ngr $(PROJECT).lso $(TMP)

diff --git a/heartbeat/raggedstone.prj b/heartbeat/raggedstone.prj
index 2c8b3d87aa7f7751c4a38e2468649fcf312631db..e0adeacf61bce8970c3cc36d43d6937d70eeb7cf 100644 (file)
--- a/heartbeat/raggedstone.prj
+++ b/heartbeat/raggedstone.prj
@@ -1,6 +1,4 @@
 verilog work "source/sync.v"
 verilog work "source/sync.v"

-verilog work "source/disp_dec.v"
-verilog work "source/wb_7seg.v"

 verilog work "source/pcidec.v"
 verilog work "source/pcidmux.v"
 
 verilog work "source/pcidec.v"
 verilog work "source/pcidmux.v"
 


@@ -12,5 +10,5 @@ vhdl work "source/pfs.vhd"
 vhdl work "source/new_pciregs.vhd"
 vhdl work "source/pcipargen.vhd"
 vhdl work "source/new_pci32tlite.vhd"
 vhdl work "source/new_pciregs.vhd"
 vhdl work "source/pcipargen.vhd"
 vhdl work "source/new_pci32tlite.vhd"

-vhdl work "source/vga_main.vhd"

 vhdl work "source/top_pci_7seg.vhd"
 vhdl work "source/top_pci_7seg.vhd"

+vhdl work "source/heartbeat.vhd"

diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 483a19f91f9fbe4cfa2bd46eaad447d3aeab9749..31d028c5174f916438f2bdc5d6798fa10af2fee2 100644 (file)
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -1,14 +1,3 @@
-NET "DISP_LED<0>"  LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<1>"  LOC = "AA20" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<2>"  LOC = "V18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<3>"  LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<4>"  LOC = "AB18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<5>"  LOC = "AA18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_LED<6>"  LOC = "W18" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<0>"  LOC = "AA17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<1>"  LOC = "U17" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<2>"  LOC = "U16" | IOSTANDARD = LVCMOS33 ;
-NET "DISP_SEL<3>"  LOC = "U14" | IOSTANDARD = LVCMOS33 ;

 NET "LED_ACCESS"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
 NET "LED_INIT"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
 NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
 NET "LED_ACCESS"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
 NET "LED_INIT"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
 NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;


@@ -60,9 +49,3 @@ NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "LED_ALIVE"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "LED_ALIVE"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;

-NET "mclk"  LOC = "E22";
-NET "red"  LOC = "E21";
-NET "grn"  LOC = "F21";
-NET "blu"  LOC = "F20";
-NET "hs"  LOC = "F19";
-NET "vs"  LOC = "G19";

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
new file mode 100644 (file)
index 0000000..76f084d
--- /dev/null
+++ b/heartbeat/source/heartbeat.vhd
@@ -0,0 +1,39 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity heartbeat is
+generic (
+       divider : integer := 33000000
+);
+
+port (
+       clk_i : in std_logic;
+       nrst_i : in std_logic;
+       led_o : out std_logic
+);   
+
+end heartbeat;
+
+architecture rtl of heartbeat is
+begin
+
+process(clk_i, nrst_i)
+variable counter : std_logic_vector(31 downto 0);
+variable state : std_logic := '0';
+begin
+
+if (clk_i'event AND clk_i = '1') then
+       if nrst_i = '0' then
+               counter := (others => '0');
+        else
+               led_o <= state;
+               counter := counter + 1;
+               if counter = divider then
+                       state := not state;
+               end if;
+       end if;
+end if;
+end process;
+end architecture;

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 6b449a78ba684c9666f5fbdcb9accf5a795801b9..73fefb15d8298f6eaf34a6a9804a2b87ba067da8 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -59,20 +59,10 @@ port (
     PCI_nSERR   : out std_logic;\r
     PCI_nINT    : out std_logic;\r
  \r
     PCI_nSERR   : out std_logic;\r
     PCI_nINT    : out std_logic;\r
  \r

-       -- 7seg\r
-    DISP_SEL                : inout std_logic_vector(3 downto 0);\r
-    DISP_LED                : out std_logic_vector(6 downto 0);\r
-       \r

        -- debug signals\r
        LED_INIT         : out std_logic;\r
        LED_ACCESS       : out std_logic;\r
        -- debug signals\r
        LED_INIT         : out std_logic;\r
        LED_ACCESS       : out std_logic;\r

-       LED_ALIVE : out std_logic;\r
-\r
-       -- vga signals\r
-       hs             : out std_logic;\r
-       vs             : out std_logic;\r
-       red, grn, blu  : out std_logic;\r
-       mclk           : in std_logic\r
+       LED_ALIVE : out std_logic\r

 \r
 );\r
 end pci_7seg;\r
 \r
 );\r
 end pci_7seg;\r


@@ -129,41 +119,12 @@ port (
        );\r
 end component;\r
 \r
        );\r
 end component;\r
 \r

-\r
-component wb_7seg_new\r
+component heartbeat\r

 port (\r
 port (\r

-   \r
-   -- General \r
-    clk_i      : in std_logic;\r
-    nrst_i        : in std_logic;\r
-    \r
-       -- Master whisbone\r
-    wb_adr_i   : in std_logic_vector(24 downto 1);     \r
-       wb_dat_o   : out std_logic_vector(15 downto 0);\r
-    wb_dat_i   : in std_logic_vector(15 downto 0);\r
-       wb_sel_i   : in std_logic_vector(1 downto 0);\r
-    wb_we_i    : in std_logic;\r
-       wb_stb_i   : in std_logic;\r
-       wb_cyc_i   : in std_logic;\r
-       wb_ack_o   : out std_logic;\r
-       wb_err_o   : out std_logic;\r
-       wb_int_o   : out std_logic;\r
-\r
-       -- 7seg\r
-    DISP_SEL   : inout std_logic_vector(3 downto 0);\r
-    DISP_LED   : out std_logic_vector(6 downto 0)\r
-\r
-   );\r
-end component;\r
-\r
-\r
-component vgaController is\r
-        Port ( mclk : in std_logic;\r
-           hs : out std_logic;\r
-           vs : out std_logic;\r
-           red : out std_logic;\r
-           grn : out std_logic;\r
-           blu : out std_logic);\r
+       clk_i : in std_logic;\r
+       nrst_i : in std_logic;\r
+       led_o : out std_logic\r
+);\r

 end component;\r
 \r
 \r
 end component;\r
 \r
 \r


@@ -188,18 +149,6 @@ end component;
 \r
 begin\r
 \r
 \r
 begin\r
 \r

-                        LED_ALIVE <= '1';\r
---+-------------------------------------------------------------------------+\r
---|  Component instances                                                                                                       |\r
---+-------------------------------------------------------------------------+\r
-\r
-       vga1: vgaController port map (mclk => mclk,\r
-               hs => hs,\r
-               vs => vs,\r
-               red => red,\r
-               grn => grn,\r
-               blu => blu);\r
-\r

 --+-----------------------------------------+\r
 --|  PCI Target                                                        |\r
 --+-----------------------------------------+\r
 --+-----------------------------------------+\r
 --|  PCI Target                                                        |\r
 --+-----------------------------------------+\r


@@ -238,22 +187,11 @@ port map(
 --|  WB-7seg                                                   |\r
 --+-----------------------------------------+\r
 \r
 --|  WB-7seg                                                   |\r
 --+-----------------------------------------+\r
 \r

-u_wb: component wb_7seg_new\r
-port map(\r
-               clk_i    =>             PCI_CLK,\r
-       nrst_i   =>             PCI_nRES,\r
-       wb_adr_i =>             wb_adr,   \r
-               wb_dat_o =>             wb_dat_out,\r
-       wb_dat_i =>             wb_dat_in,\r
-               wb_sel_i =>             wb_sel,\r
-       wb_we_i  =>     wb_we,\r
-               wb_stb_i =>             wb_stb,\r
-               wb_cyc_i =>             wb_cyc,\r
-               wb_ack_o =>             wb_ack,\r
-               wb_err_o =>             wb_err,\r
-               wb_int_o =>             wb_int,\r
-               DISP_SEL =>             DISP_SEL,\r
-               DISP_LED =>             DISP_LED\r
+my_heartbeat: component heartbeat\r
+port map( \r
+       clk_i => PCI_CLK,\r
+       nrst_i => PCI_nRES,\r
+       led_o => LED_ALIVE\r

 );\r
 \r
 end pci_7seg_arch;\r
 );\r
 \r
 end pci_7seg_arch;\r