connect LEDs on IDE board to main FPGA and let them blink

diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 9f9ac54fe32baab9276af50efa887b64272e4361..57b59c49c5c55afa7d2346375a8cccc1716c329a 100644 (file)
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -50,3 +50,7 @@ NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
 NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
+NET "IDE1"  LOC = "Y1" | IOSTANDARD = LVCMOS33 ;
+NET "IDE2"  LOC = "M6" | IOSTANDARD = LVCMOS33 ;
+NET "IDE3"  LOC = "M5" | IOSTANDARD = LVCMOS33 ;
+NET "IDE4"  LOC = "U2" | IOSTANDARD = LVCMOS33 ;

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 03a465bd9ed843684ec096894e4fbddf74a5745e..cae72cd9a4e4f6042fa4cac8a6a5647e8f26e0cc 100644 (file)
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -14,7 +14,11 @@ port (
        led2_o : out std_logic;
        led3_o : out std_logic;
        led4_o : out std_logic;
-       led5_o : out std_logic
+       led5_o : out std_logic;
+       led6_o : out std_logic;
+       led7_o : out std_logic;
+       led8_o : out std_logic;
+       led9_o : out std_logic
 );   
 
 end heartbeat;
@@ -24,7 +28,7 @@ begin
 
 process(clk_i, nrst_i)
 variable counter : std_logic_vector(31 downto 0);
-variable state : std_logic_vector(3 downto 0) := "0001";
+variable state : std_logic_vector(7 downto 0) := "00000001";
 variable direction : std_logic := '0';
 begin
 
@@ -36,9 +40,13 @@ if (rising_edge(clk_i)) then
                led3_o <= state(1);
                led4_o <= state(2);
                led5_o <= state(3);
+               led6_o <= state(4);
+               led7_o <= state(5);
+               led8_o <= state(6);
+               led9_o <= state(7);
                counter := counter + 1;
                if counter = divider then
-                       if state(3) = '1' then
+                       if state(7) = '1' then
                                direction := '1';
                        end if;
 
@@ -47,11 +55,11 @@ if (rising_edge(clk_i)) then
                        end if;
 
                        if direction = '0' then
-                               state(3 downto 1) := state(2 downto 0);
+                               state(7 downto 1) := state(6 downto 0);
                                state(0) := '0';
                        else
-                               state(2 downto 0) := state(3 downto 1);
-                               state(3) := '0';
+                               state(6 downto 0) := state(7 downto 1);
+                               state(7) := '0';
                        end if;
                        counter := (others => '0');
                end if;

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index b0739895d536833d7a1a5db286d478bb755cade8..c7982941f1283337f185315ab2d796ae4ec64273 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -63,7 +63,11 @@ port (
        LED3    : out std_logic;\r
        LED2    : out std_logic;\r
        LED4            : out std_logic;\r
-       LED5            : out std_logic\r
+       LED5            : out std_logic;\r
+       IDE1    : out std_logic;\r
+       IDE2    : out std_logic;\r
+       IDE3    : out std_logic;\r
+       IDE4    : out std_logic\r
 \r
 );\r
 end raggedstone;\r
@@ -127,7 +131,11 @@ port (
        led2_o : out std_logic;\r
        led3_o : out std_logic;\r
        led4_o : out std_logic;\r
-       led5_o : out std_logic\r
+       led5_o : out std_logic;\r
+       led6_o : out std_logic;\r
+       led7_o : out std_logic;\r
+       led8_o : out std_logic;\r
+       led9_o : out std_logic\r
 );\r
 end component;\r
 \r
@@ -198,7 +206,11 @@ port map(
        led2_o => LED2,\r
        led3_o => LED3,\r
        led4_o => LED4,\r
-       led5_o => LED5\r
+       led5_o => LED5,\r
+       led6_o => IDE1,\r
+       led7_o => IDE2,\r
+       led8_o => IDE3,\r
+       led9_o => IDE4\r
 );\r
 \r
 end raggedstone_arch;\r

diff --git a/ideboard/.cvsignore b/ideboard/.cvsignore
new file mode 100644 (file)
index 0000000..c9ea511
--- /dev/null
+++ b/ideboard/.cvsignore
@@ -0,0 +1,33 @@
+_impact*
+_ngo
+ideboard-xcf02s.mcs
+ideboard-xcf02s.prm
+ideboard-xcf04s.mcs
+ideboard-xcf04s.prm
+ideboard.bgn
+ideboard.bit
+ideboard.bld
+ideboard.drc
+ideboard.lso
+ideboard.ncd
+ideboard.ngc
+ideboard.ngd
+ideboard.ngr
+ideboard.pad
+ideboard.par
+ideboard.pcf
+ideboard.syr
+ideboard.twr
+ideboard.twx
+ideboard.unroutes
+ideboard.xpi
+ideboard_map.map
+ideboard_map.mrp
+ideboard_map.ncd
+ideboard_map.ngm
+ideboard_pad.csv
+ideboard_pad.txt
+ideboard_summary.xml
+ideboard_usage.xml
+timing.twr
+xst

diff --git a/ideboard/source/ide.vhd b/ideboard/source/ide.vhd
index 20cc961409b7f23beba36de477b1b6244148e92f..3ddc5c173c38ae37c2ec22f7f868aff2289acb3f 100644 (file)
--- a/ideboard/source/ide.vhd
+++ b/ideboard/source/ide.vhd
@@ -46,10 +46,10 @@ entity ide is
           IDE_CHIP_SELECT_3P : out std_logic;
           IDE_IRQ : out std_logic;
           IDE_ACTIVITY : out std_logic;
-          FPGA1 : out std_logic;
-          FPGA2 : out std_logic;
-          FPGA3 : out std_logic;
-          FPGA4 : out std_logic;
+          FPGA1 : in std_logic;
+          FPGA2 : in std_logic;
+          FPGA3 : in std_logic;
+          FPGA4 : in std_logic;
           FPGA5 : out std_logic;
           FPGA6 : out std_logic;
           FPGA7 : out std_logic;
@@ -88,9 +88,9 @@ end ide;
 architecture Behavioral of ide is
 
 begin
-       LED_1 <= '1';
-       LED_2 <= '1';
-       LED_3 <= '1';
-       LED_4 <= '0';
+       LED_1 <= FPGA1;
+       LED_2 <= FPGA2;
+       LED_3 <= FPGA3;
+       LED_4 <= FPGA4;
 end Behavioral;