more chipscope signals

diff --git a/ethernet/ethernet.xst b/ethernet/ethernet.xst
index 41925824d2464ddb0c76ff94aa356dca68076a05..48caa9cd36f37997c5274af558697056ada052ce 100644 (file)
--- a/ethernet/ethernet.xst
+++ b/ethernet/ethernet.xst
@@ -8,7 +8,7 @@ run
 -top ethernet
 -opt_mode Speed
 -opt_level 1
 -top ethernet
 -opt_mode Speed
 -opt_level 1

--iuc NO
+-iuc YES

 -lso ethernet.lso
 -keep_hierarchy NO
 -glob_opt AllClockNets
 -lso ethernet.lso
 -keep_hierarchy NO
 -glob_opt AllClockNets

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 1617eee849ab9d826f2c772d6e921d5bd7122aae..9bb2d48c81aa88abf73c4055bd0b0b33869ca8e5 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -230,6 +230,7 @@ signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);

+signal mdc_pad_o_watch : std_logic;

 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);


@@ -269,10 +270,18 @@ wb_clk_i <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
 data(40 downto 33) <= wbm_adr_o (7 downto 0);
 
 data(31 downto 0)  <= wbm_adr_o;
 data(40 downto 33) <= wbm_adr_o (7 downto 0);

-data(63 downto 41) <= (others => '0');
+data(41) <= MD_PAD_IO;
+data(42) <= md_pad_o;
+data(43) <= md_padoe_o;
+data(44) <= mdc_pad_o_watch;
+MDC_PAD_O <= mdc_pad_o_watch;
+data(63 downto 45) <= (others => '0');

 
 trig0(31 downto 0) <= (
        0 => wb_stb_i,
 
 trig0(31 downto 0) <= (
        0 => wb_stb_i,

+       1 => MD_PAD_IO,
+       2 => md_pad_o,
+       3 => md_padoe_o,

        others => '0'
 );
 
        others => '0'
 );
 


@@ -379,7 +388,7 @@ Inst_eth_top: eth_top PORT MAP(
         mrxerr_pad_i => MRXERR_PAD_I,
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,
         mrxerr_pad_i => MRXERR_PAD_I,
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,

-        mdc_pad_o => MDC_PAD_O,
+        mdc_pad_o => mdc_pad_o_watch,

         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,