]> cvs.zerfleddert.de Git - raggedstone/commitdiff
a bit better
authormichael <michael>
Wed, 21 Mar 2007 14:01:16 +0000 (14:01 +0000)
committermichael <michael>
Wed, 21 Mar 2007 14:01:16 +0000 (14:01 +0000)
ethernet/phydcm.xaw
ethernet/source/phydcm.vhd
ethernet/source/top.vhd

index 262cfc58c5e3888930dd45463046272421481df5..573e496d4d07075ec2f58127b526cf388c6925a3 100644 (file)
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.4e
-$9cx73=(`fgn#`glh`go+Wg`olnxxb`j/scdc`bt|fdn#hzgeslfp*bde'rj{<5?4:2-437<9;1:=55>6&j;4=6538R:7?:42/046>45:282:6=?.2206>54?23%=#>=i69BVFNPAS;<7L\XZ^MMH\YDIZIJHD@H_BNH5==FZ^PTCCBV_BNHMKYBP]OYBLB>5:CQS_YHFESTOAEFN^TBHPC6j2KY[WQ@NM[\@FKX[^C_OEGAG^AOO46<I[]QSB@CY^FGVZE7991J^ZTPOONZ[ABUWJ;:=6O]W[]LJI_XLMXTOAE>6:CQS_YHFESTHI\PFMKSBIIW9<1J^ZTPOONZ[CDXMQ^N^COC139BVR\XGGFRSD@\T^LVI`=FZ^PTCCBV_QO@@43<I[]QSB@CY^PFW@RXDFMBO<64ASUY[JHKQV\J@DJPDGQ\IJBBi2KX_BMPWHVKb>GPRVIGGO[ITXRF540<I^PTOAEMUGVZT@7XFFOOEY?<;@UY[FJLWF__\XZPTXRFg>GPRVLGCZZVPD:8ER\XXHX_h6OXZ^QZJQNSGFF?7OA[H59AQCA33JF@<55LLJ2\FP@b3JF@<RLZFF]JJVR?3JF@<RAZT79@HN7?8?1H@F<8049@HN4_02IGG?V>8178GIM>8<1H@FJYc:AOOAPXL@\BHH;4CMIEF==DDBLISD@:;BNHB]><KEAMT<6?9:AOOC^XJ\Lm7NBDFY]AQCAXAGY_o6MCKGZ\@LPNLLo0OAEIX^OVHQOWDP30OAEIX^MVP0=DDBCE=<5LLJKM[AOQAMOTNTQ=b:AOOLHXAK_MK<>4CMIJJZOE]OMTEC][f:AOOLHXAK_MKRAZT99@HNOIW@Dh7NBDIO]SAWOHLl1H@FGA_RP@[Q_WM880OAE@UU]SLDUBWZBBJYm4CMI\B@CCJHI@56M@MLKWP@B03JXNMYKK3:F@I==CKDUBB^Zk;EGPO@QXIM@^_Y?=;EDP[CTBY\OEOTQBOEGb?AJKWHDOSKV>2:FOHZ@UMX_NBNWPMNFF1>BT[LD:96JZTX]@]FJBWJEY^HM[INL4?AYQIE_N46KWTDPMEIg<NHI_C_WPJG78BDJTM01MNR]@USAFg>@BMMHJOFQMUG;8BLHX]GC__l5IOTV\QKOS[h1MCXZPV@NVA4=N=2CIYKI7;HLWAWHFD8;0FDZ[ES]JJUSSW]S[In5EIUVFVZVL:YAh7GG[TDP\RDJRM?1GCLJJD79OKFMBLh1GCNEJD^MVP6=KG^90AETm;L]BJAYCWZ^Y;6CPV@NVA2=IM]]D^F:4NNLF5>I?3FLOH_M_Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][6:PPPZOIj2YBKHV[ESLBH3=TAGMGIn5\T@PWQUYPI@^=7^ZNTTQ26>U^[]OFS^WACIPLJJST;2^D\95[RTG;?PUBWK_MK45ZSD]AQCAT=2\BIZ?m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB?6V\T79[`gYNl8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`:;Z294X3<S90<Q95nrvx0?aejj2|n~~g`n!3-41=q`mf:<6vl3r3645+ao=?=!9sO@q1a?EF\7f83L187?tS569<0<??3;8>>hm1;03<3`|f1;1=6`72;68 =6=?l1v_9=5848;3?74::li=7<?ab`8W0e=0<03;7?<22da5?47m:>0_9=5848;3?74::li=7<?e408`=3=83;1=v];4;:6>=1=9:88jo?521:5b>pS?j0;6<4>:`yP01<?=32<6<==3g`2>76?>o1i;54?:187>d}#m32=7)<?:9:8 77=001/>?48f:&4`?b<j=<1<7?<:183\7f!0e2=?0(k4=e:&24?133-;96?;4$01960=#9=0956*>5;06?!712?<0(<95759'5=<43-;26;:4$0c915=#9k09?6*;2;48 7`=?2.8:7o4$259=>"4i3?;7)=i:c9'05<3m2.?=78;;%64>21<,=n1m6*;8;7e?!2f2<l0(9m5789'0c<23-?:6864$41925=#==0=<6*:5;68 0?=>81/:?46;%44>4=#?<0><6*8a;5a?!762j1/=k4;9:&6f?4<,<k146g<9;29 3g=0:1/:n489:9j75<72-<j65=4$7a93<=<a>;1<7*9a;:0?!0d2>307d8i:18'2d<?;2.=5796;:k44?6=,?k14>5+6884=>=n>m0;6)8n:918 3?=?010e9l50;&5e?>43-<26:74;n06>5<#>h03?6*9c;5:?!7c2;>0(<k55398k7b=83.=m76<;:m1=?6=,?k14>54o3c94?"1i32876a=e;29 3g=0:10c?l50;&5e?>432e9o7>5$7c9<6=<g:81<7*9a;:0?!0d2>30(<j52598k65=83.=m76<;:m42?6=,?k1495+6984=>=h=m0;6)8n:918 3e=?010c;k50;&5e?>432wi?n4?:383>5}#>k0>;6g:6;29 3g=0:1/:n489:9l20<72-<j65=4$7a93<=<uk8<6=4=:183\7f!0e2;>0e8850;&5e?>43-<h6:74;n46>5<#>h03?6*9c;5:?>{e;<0;6?4?:1y'2g<5<2c>:7>5$7c9<6=#>j0<565`6483>!0f2190(;m57898yv5e2909w0:9:2;896e=><1/=n4<d:\7fp74<72;q68;4<0:?13?023-;h6?64}r51>5<6s4>=6:?4$61913=z{;<1<7<t=54960=::>0>:6s|3583>7}:<?08>63<5;75?xu2m3:1=v3;6;7g?!142??0q~=j:182\7f85d2<<0(:=5579~w6>=83;p1>;5649'36<1=2wx?i4?:1y'36<1=2wx>54?:1y'36<1=2wvb?950;3xyk4?290:wp`=9;295~{i:h0;6<urn3`94?7|ug8h6=4>{|l1`?6=9rwe>h4?:0y~j7`=83;pqc=?:182\7fx{zuIJHw>l5165;b5dfuIJIw=sO@Qy~DE
\ No newline at end of file
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\ No newline at end of file
index efec74a17565f26aed7584b0cab3496ba9379185..a5db448e54f5889352f3352705c2a6953f0ca299 100644 (file)
@@ -7,7 +7,7 @@
 -- \   \   \/     Version : 9.1.02i
 --  \   \         Application : xaw2vhdl
 --  /   /         Filename : phydcm.vhd
--- /___/   /\     Timestamp : 03/21/2007 14:47:39
+-- /___/   /\     Timestamp : 03/21/2007 14:56:33
 -- \   \  /  \ 
 --  \___\/\___\ 
 --
@@ -26,30 +26,23 @@ library UNISIM;
 use UNISIM.Vcomponents.ALL;
 
 entity phydcm is
-   port ( CLKIN_IN        : in    std_logic; 
-          RST_IN          : in    std_logic; 
-          CLKFX_OUT       : out   std_logic; 
-          CLKIN_IBUFG_OUT : out   std_logic; 
-          CLK0_OUT        : out   std_logic; 
-          LOCKED_OUT      : out   std_logic);
+   port ( CLKIN_IN   : in    std_logic; 
+          RST_IN     : in    std_logic; 
+          CLKFX_OUT  : out   std_logic; 
+          CLK0_OUT   : out   std_logic; 
+          LOCKED_OUT : out   std_logic);
 end phydcm;
 
 architecture BEHAVIORAL of phydcm is
-   signal CLKFB_IN        : std_logic;
-   signal CLKFX_BUF       : std_logic;
-   signal CLKIN_IBUFG     : std_logic;
-   signal CLK0_BUF        : std_logic;
-   signal GND_BIT         : std_logic;
+   signal CLKFB_IN   : std_logic;
+   signal CLKFX_BUF  : std_logic;
+   signal CLK0_BUF   : std_logic;
+   signal GND_BIT    : std_logic;
    component BUFG
       port ( I : in    std_logic; 
              O : out   std_logic);
    end component;
    
-   component IBUFG
-      port ( I : in    std_logic; 
-             O : out   std_logic);
-   end component;
-   
    -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
    -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
    component DCM
@@ -91,16 +84,11 @@ architecture BEHAVIORAL of phydcm is
    
 begin
    GND_BIT <= '0';
-   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
    CLK0_OUT <= CLKFB_IN;
    CLKFX_BUFG_INST : BUFG
       port map (I=>CLKFX_BUF,
                 O=>CLKFX_OUT);
    
-   CLKIN_IBUFG_INST : IBUFG
-      port map (I=>CLKIN_IN,
-                O=>CLKIN_IBUFG);
-   
    CLK0_BUFG_INST : BUFG
       port map (I=>CLK0_BUF,
                 O=>CLKFB_IN);
@@ -121,7 +109,7 @@ begin
             PHASE_SHIFT => 0,
             STARTUP_WAIT => FALSE)
       port map (CLKFB=>CLKFB_IN,
-                CLKIN=>CLKIN_IBUFG,
+                CLKIN=>CLKIN_IN,
                 DSSEN=>GND_BIT,
                 PSCLK=>GND_BIT,
                 PSEN=>GND_BIT,
index 480de0a9aa128293e2b85699971bef38ec295a42..1617eee849ab9d826f2c772d6e921d5bd7122aae 100644 (file)
@@ -175,7 +175,6 @@ component phydcm is
 port ( CLKIN_IN        : in    std_logic;
        RST_IN          : in    std_logic;
        CLKFX_OUT       : out   std_logic;
-       CLKIN_IBUFG_OUT : out   std_logic;
        CLK0_OUT        : out   std_logic;
        LOCKED_OUT      : out   std_logic);
 end component;
@@ -406,10 +405,9 @@ eth_dcm : phydcm
 port map (
        CLKIN_IN => PCI_CLOCK,
        RST_IN => not PCI_RSTn,
-       CLKFX_OUT => PHY_CLOCK
---     CLKIN_IBUFG_OUT
---     CLK0_OUT
---     LOCKED_OUT
+       CLKFX_OUT => PHY_CLOCK,
+       CLK0_OUT => open,
+       LOCKED_OUT => open
        );
 
 end architecture ethernet_arch;
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