fifo_data_i : in std_logic_vector(7 downto 0);\r
fifo_data_o : out std_logic_vector(7 downto 0);\r
\r
- fifo_we_out : out std_logic;\r
- fifo_re_out : out std_logic\r
+ fifo_we_o : out std_logic;\r
+ fifo_re_o : out std_logic\r
);\r
end component;\r
\r
fifo_data_i => fifo_dout,\r
fifo_data_o => fifo_din,\r
\r
- fifo_we_out => fifo_we,\r
- fifo_re_out => fifo_re\r
+ fifo_we_o => fifo_we,\r
+ fifo_re_o => fifo_re\r
);\r
\r
my_heartbeat: component heartbeat\r