component for dram

diff --git a/dhwk_old/source/generic_dpram.v b/dhwk_old/source/generic_dpram.v
index 816122e6c8e23234fcab6c94b98da4f034072b25..e75a91ec25193d529e68c27a0aee66df59cc7c68 100644 (file)
--- a/dhwk_old/source/generic_dpram.v
+++ b/dhwk_old/source/generic_dpram.v
@@ -66,7 +66,10 @@
 // CVS Revision History
 //
 // $Log: generic_dpram.v,v $
 // CVS Revision History
 //
 // $Log: generic_dpram.v,v $

-// Revision 1.2  2007-02-11 22:15:39  sithglan
+// Revision 1.3  2007-02-11 22:18:24  michael
+// component for dram
+//
+// Revision 1.2  2007/02/11 22:15:39  sithglan

 // define xilinix and fpga
 //
 // Revision 1.1  2007/02/11 22:05:26  sithglan
 // define xilinix and fpga
 //
 // Revision 1.1  2007/02/11 22:05:26  sithglan


@@ -118,8 +121,8 @@ module generic_dpram(
        //
        // Default address and data buses width
        //
        //
        // Default address and data buses width
        //

-       parameter aw = 5;  // number of bits in address-bus
-       parameter dw = 16; // number of bits in data-bus
+       parameter aw = 12;  // number of bits in address-bus
+       parameter dw = 8; // number of bits in data-bus

 
        //
        // Generic synchronous double-port RAM interface
 
        //
        // Generic synchronous double-port RAM interface

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index dbb54e9021612558ff3ab5a72581f03c1399840c..841f82ad751ef1a9a6fe9cf21a22e4c29e1d139b 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -152,6 +152,23 @@ port (
 );\r
 end component;\r
 \r
 );\r
 end component;\r
 \r

+component generic_dpram\r
+port (\r
+       rclk            : in std_logic;\r
+       rrst            : in std_logic;\r
+       rce             : in std_logic;\r
+       oe              : in std_logic;\r
+       raddr           : in std_logic_vector(11 downto 0);\r
+       do              : out std_logic_vector(7 downto 0);\r
+       wclk            : in std_logic;\r
+       wrst            : in std_logic;\r
+       wce             : in std_logic;\r
+       we              : in std_logic;\r
+       waddr           : in std_logic_vector(11 downto 0);\r
+       di              : in std_logic_vector(7 downto 0);\r
+);\r
+end component;\r
+\r

 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    CONSTANTS                                                                       |\r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    CONSTANTS                                                                       |\r