move address register

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index dc481074584007208fe1c245c9749431bb39e3cf..d4233c634c95c3190e515ba7005714ecdcdf81be 100644 (file)
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -18,7 +18,6 @@ vhdl work "source/Io_mux.vhd"
 vhdl work "source/CONT_FSM.vhd"
 vhdl work "source/COMM_FSM.vhd"
 vhdl work "source/COMM_DEC.vhd"
 vhdl work "source/CONT_FSM.vhd"
 vhdl work "source/COMM_FSM.vhd"
 vhdl work "source/COMM_DEC.vhd"

-vhdl work "source/Addr_regi.vhd"

 vhdl work "source/vergleich.vhd"
 vhdl work "source/steuerung.vhd"
 vhdl work "source/reg_io.vhd"
 vhdl work "source/vergleich.vhd"
 vhdl work "source/steuerung.vhd"
 vhdl work "source/reg_io.vhd"


@@ -40,3 +39,4 @@ vhdl work "source/MESS_1_TB.vhd"
 vhdl work "source/INTERRUPT.vhd"
 vhdl work "source/top.vhd"
 vhdl work "source/ven_rev_id.vhd"
 vhdl work "source/INTERRUPT.vhd"
 vhdl work "source/top.vhd"
 vhdl work "source/ven_rev_id.vhd"

+vhdl work "source/pci/address_register.vhd"

diff --git a/dhwk/source/Addr_regi.vhd b/dhwk/source/Addr_regi.vhd
deleted file mode 100644 (file)
index 143c7b5..0000000
--- a/dhwk/source/Addr_regi.vhd
+++ /dev/null
@@ -1,43 +0,0 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: ADDR_REG.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity ADDR_REGI is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in             std_logic;\r
-       PCI_RSTn                        :in             std_logic;\r
-       LOAD_ADDR_REG   :in             std_logic;\r
-       AD_REG                          :in             std_logic_vector (31 downto 0);\r
-       ADDR_REG                        :out    std_logic_vector (31 downto 0)\r
-  );\r
-end entity ADDR_REGI;\r
-\r
-architecture ADDR_REGI_DESIGN of ADDR_REGI is\r
-\r
-       signal  REG_ADDR        :std_logic_vector (31 downto 0); \r
-\r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    REG_ADDR        <= X"00000000";\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if LOAD_ADDR_REG = '1' then\r
-                                               REG_ADDR        <=      AD_REG;\r
-\r
-                       else    REG_ADDR        <=      REG_ADDR;\r
-                       end if;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       ADDR_REG        <=      REG_ADDR;\r
-\r
-end architecture ADDR_REGI_DESIGN;\r

diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
index 38f23567a5158f9b6d11bd76ae978dbb8ccf5b95..564d8bb6337261c42158713b19f5a112ff6d2cc2 100644 (file)
--- a/dhwk/source/io_mux_reg.vhd
+++ b/dhwk/source/io_mux_reg.vhd
@@ -38,7 +38,7 @@ architecture SCHEMATIC of IO_MUX_REG is
    signal  IO_DATA : std_logic_vector (31 downto 0);\r
    signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
 \r
    signal  IO_DATA : std_logic_vector (31 downto 0);\r
    signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
 \r

-   component ADDR_REGI\r
+   component ADDRESS_REGISTER\r

       Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
              LOAD_ADDR_REG : In    std_logic;\r
              PCI_CLOCK : In    std_logic;\r
       Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
              LOAD_ADDR_REG : In    std_logic;\r
              PCI_CLOCK : In    std_logic;\r


@@ -77,7 +77,7 @@ begin
 \r
    AD_REG <= AD_REG_DUMMY;\r
 \r
 \r
    AD_REG <= AD_REG_DUMMY;\r
 \r

-   I5 : ADDR_REGI\r
+   I5 : ADDRESS_REGISTER\r

       Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                  LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
                  PCI_RSTn=>PCI_RSTn,\r
       Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                  LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
                  PCI_RSTn=>PCI_RSTn,\r

diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd
new file mode 100644 (file)
index 0000000..11602a9
--- /dev/null
+++ b/dhwk/source/pci/address_register.vhd
@@ -0,0 +1,39 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: ADDR_REG.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity ADDRESS_REGISTER is\r
+       port (\r
+                PCI_CLOCK      :in     std_logic;\r
+                PCI_RSTn       :in     std_logic;\r
+                LOAD_ADDR_REG  :in     std_logic;\r
+                AD_REG         :in     std_logic_vector (31 downto 0);\r
+                ADDR_REG       :out    std_logic_vector (31 downto 0)\r
+        );\r
+end entity ADDRESS_REGISTER;\r
+\r
+architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is\r
+       signal  REG_ADDR        :std_logic_vector (31 downto 0); \r
+begin \r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then\r
+                        REG_ADDR       <= X"00000000";\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+                       if LOAD_ADDR_REG = '1' then\r
+                                REG_ADDR       <=      AD_REG;\r
+                       else\r
+                                REG_ADDR       <=      REG_ADDR;\r
+                       end if;\r
+               end if;\r
+       end process;\r
+\r
+       ADDR_REG        <=      REG_ADDR;\r
+\r
+end architecture ADDR_REGI_DESIGN;\r