-dpram component

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 67fe5aa843739e8623d6436af03114a27d43a196..0e03a31b223e9ce5216ccf579b7f4b54d38b50fe 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,34 +109,16 @@ port (
 );\r
 end component;\r
 \r
-component generic_dpram\r
-port (\r
-       rclk            : in std_logic;\r
-       rrst            : in std_logic;\r
-       rce             : in std_logic;\r
-       oe              : in std_logic;\r
-       raddr           : in std_logic_vector(11 downto 0);\r
-       do              : out std_logic_vector(7 downto 0);\r
-       wclk            : in std_logic;\r
-       wrst            : in std_logic;\r
-       wce             : in std_logic;\r
-       we              : in std_logic;\r
-       waddr           : in std_logic_vector(11 downto 0);\r
-       di              : in std_logic_vector(7 downto 0)\r
-);\r
-end component;\r
-\r
-\r
-       signal  wb_adr :                std_logic_vector(24 downto 1);   \r
-       signal  wb_dat_out :    std_logic_vector(15 downto 0);\r
-       signal  wb_dat_in :             std_logic_vector(15 downto 0);\r
-       signal  wb_sel :                std_logic_vector(1 downto 0);\r
-       signal  wb_we :                 std_logic;\r
-       signal  wb_stb :                std_logic;\r
-       signal  wb_cyc :                std_logic;\r
-       signal  wb_ack :                std_logic;\r
-       signal  wb_err :                std_logic;\r
-       signal  wb_int :                std_logic;\r
+signal         wb_adr :                std_logic_vector(24 downto 1);   \r
+signal wb_dat_out :    std_logic_vector(15 downto 0);\r
+signal         wb_dat_in :             std_logic_vector(15 downto 0);\r
+signal wb_sel :                std_logic_vector(1 downto 0);\r
+signal  wb_we :                        std_logic;\r
+signal wb_stb :                std_logic;\r
+signal wb_cyc :                std_logic;\r
+signal wb_ack :                std_logic;\r
+signal wb_err :                std_logic;\r
+signal wb_int :                std_logic;\r
 \r
 \r
 begin\r