INTSTYLE := silent
SOURCES = $(wildcard sources/*.v source/*.vhd)
+PART ?= xc3s1500-fg456-4
+TARGET ?= bit
ifdef DRIVER
PRELOAD = LD_PRELOAD=$(DRIVER)
endif
-all: $(PROJECT).bit final
+all: $(PROJECT).$(TARGET) final
log:
time make all &>build.log
ngdbuild: $(PROJECT).ngd
-$(PROJECT).ngc: $(SOURCES) $(PROJECT).prj $(PROJECT).ucf $(PROJECT).ut $(PROJECT).xst
+$(PROJECT).ngc: $(SOURCES) $(PROJECT).prj $(PROJECT).ucf $(PROJECT).xst
@# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1
echo work > $(PROJECT).lso
xst -intstyle $(INTSTYLE) -ifn $(PROJECT).xst -ofn $(PROJECT).syr
@#cat $(PROJECT).syr
$(PROJECT).ngd: $(PROJECT).ngc
- ngdbuild -intstyle $(INTSTYLE) -dd "$(PWD)/_ngo" -nt timestamp -uc $(PROJECT).ucf -p xc3s1500-fg456-4 $(PROJECT).ngc $(PROJECT).ngd
+ ngdbuild -intstyle $(INTSTYLE) -dd "$(PWD)/_ngo" -nt timestamp -uc $(PROJECT).ucf -p $(PART) $(PROJECT).ngc $(PROJECT).ngd
$(PROJECT)_map.ngm $(PROJECT).pcf: $(PROJECT).ngd
- map -intstyle $(INTSTYLE) -p xc3s1500-fg456-4 -cm area -pr b -k 4 -c 100 -o $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf
+ map -intstyle $(INTSTYLE) -p $(PART) -cm area -pr b -k 4 -c 100 -o $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf
$(PROJECT).ncd: $(PROJECT)_map.ngm $(PROJECT).pcf
@#par -w -intstyle $(INTSTYLE) -ol std -n 4 -t 1 $(PROJECT)_map.ncd $(PROJECT).dir $(PROJECT).pcf
@#cat $(PROJECT).drc
@#cat $(PROJECT).bgn
+$(PROJECT).vm6: $(PROJECT).ngd
+ cpldfit -intstyle $(INTSTYLE) -p $(PART) -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper $(PROJECT).ngd
+
+$(PROJECT).jed: $(PROJECT).vm6
+ hprep6 -intstyle $(INTSTYLE) -s IEEE1149 -n $(PROJECT) -i $(PROJECT)
+
$(PROJECT)-xcf02s.mcs $(PROJECT)-xcf04s.mcs: $(PROJECT).bit
promgen -intstyle $(INTSTYLE) -w -p mcs -u 0 $(PROJECT) -o $(PROJECT)-xcf02s $(PROJECT)-xcf04s -x xcf02s xcf04s
clean:
@rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd \
*.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso *.prm *.mcs _impact* \
+ *.vm6 *.jed *.gyd *.mfd *.pnx *.rpt *.err \
$(PROJECT)_map.* $(PROJECT)_pad.* \
_ngo xst \
build.log \
--- /dev/null
+PROJECT := ideboard
+PART := xc9572xl-7-TQ100
+TARGET := jed
+
+include ../common/Makefile.common
--- /dev/null
+vhdl work "source/ide.vhd"
--- /dev/null
+NET "LED_1" LOC = "P70" ;
+NET "LED_2" LOC = "P68" ;
+NET "LED_3" LOC = "P67" ;
+NET "LED_4" LOC = "P66" ;
+NET "IDE_DATA<0>" LOC = "P91" ;
+NET "IDE_DATA<1>" LOC = "P93" ;
+NET "IDE_DATA<2>" LOC = "P95" ;
+NET "IDE_DATA<3>" LOC = "P97" ;
+NET "IDE_DATA<4>" LOC = "P1" ;
+NET "IDE_DATA<5>" LOC = "P4" ;
+NET "IDE_DATA<6>" LOC = "P8" ;
+NET "IDE_DATA<7>" LOC = "P10" ;
+NET "IDE_DATA<8>" LOC = "P11" ;
+NET "IDE_DATA<9>" LOC = "P9" ;
+NET "IDE_DATA<10>" LOC = "P6" ;
+NET "IDE_DATA<11>" LOC = "P3" ;
+NET "IDE_DATA<12>" LOC = "P99" ;
+NET "IDE_DATA<13>" LOC = "P96" ;
+NET "IDE_DATA<14>" LOC = "P94" ;
+NET "IDE_DATA<15>" LOC = "P92" ;
+NET "IDE_ADDR<0>" LOC = "P77" ;
+NET "IDE_ADDR<1>" LOC = "P78" ;
+NET "IDE_ADDR<2>" LOC = "P76" ;
+NET "IDE_RESET" LOC = "P12" ;
+NET "IDE_IO_READ" LOC = "P87" ;
+NET "IDE_GPIO_DMA66_DETECT" LOC = "P79" ;
+NET "IDE_DDRQ" LOC = "P90" ;
+NET "IDE_CABLE_SELECT" LOC = "P86" ;
+NET "IDE_IO_WRITE" LOC = "P89" ;
+NET "IDE_IOC_HRDY" LOC = "P85" ;
+NET "IDE_DDACK" LOC = "P82" ;
+NET "IDE_CHIP_SELECT_1P" LOC = "P72" ;
+NET "IDE_CHIP_SELECT_3P" LOC = "P74" ;
+NET "IDE_IRQ" LOC = "P81" ;
+NET "IDE_ACTIVITY" LOC = "P71" ;
+NET "FPGA1" LOC = "P65" ;
+NET "FPGA2" LOC = "P59" ;
+NET "FPGA3" LOC = "P58" ;
+NET "FPGA4" LOC = "P64" ;
+NET "FPGA5" LOC = "P63" ;
+NET "FPGA6" LOC = "P61" ;
+NET "FPGA7" LOC = "P60" ;
+NET "FPGA8" LOC = "P42" ;
+NET "FPGA9" LOC = "P22" ;
+NET "FPGA10" LOC = "P17" ;
+NET "FPGA11" LOC = "P15" ;
+NET "FPGA12" LOC = "P14" ;
+NET "FPGA13" LOC = "P20" ;
+NET "FPGA14" LOC = "P18" ;
+NET "FPGA15" LOC = "P13" ;
+NET "FPGA16" LOC = "P16" ;
+NET "OUT1" LOC = "P56" ;
+NET "OUT2" LOC = "P54" ;
+NET "OUT3" LOC = "P52" ;
+NET "OUT4" LOC = "P49" ;
+NET "OUT5" LOC = "P41" ;
+NET "OUT6" LOC = "P39" ;
+NET "OUT7" LOC = "P37" ;
+NET "OUT8" LOC = "P35" ;
+NET "OUT9" LOC = "P32" ;
+NET "OUT10" LOC = "P30" ;
+NET "OUT11" LOC = "P29" ;
+NET "OUT12" LOC = "P27" ;
+NET "OUT13" LOC = "P36" ;
+NET "OUT14" LOC = "P33" ;
+NET "OUT15" LOC = "P28" ;
+NET "OUT16" LOC = "P25" ;
+NET "OUT17" LOC = "P40" ;
+NET "OUT18" LOC = "P53" ;
+NET "OUT19" LOC = "P50" ;
+NET "OUT20" LOC = "P55" ;
--- /dev/null
+set -xsthdpdir "./xst"
+run
+-ifn ideboard.prj
+-ifmt mixed
+-ofn ideboard
+-ofmt NGC
+-p xc9500xl
+-top ide
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso ideboard.lso
+-keep_hierarchy YES
+-rtlview Yes
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-mux_extract YES
+-resource_sharing YES
+-iobuf YES
+-pld_mp YES
+-pld_xp YES
+-pld_ce YES
+-wysiwyg NO
+-equivalent_register_removal YES
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:50:29 03/05/2007
+-- Design Name:
+-- Module Name: ide - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ide is
+ Port ( LED_1 : out STD_LOGIC;
+ LED_2 : out STD_LOGIC;
+ LED_3 : out STD_LOGIC;
+ LED_4 : out STD_LOGIC;
+ IDE_DATA : out std_logic_vector(15 downto 0);
+ IDE_ADDR : out std_logic_vector(2 downto 0);
+ IDE_RESET : out std_logic;
+ IDE_IO_READ : out std_logic;
+ IDE_GPIO_DMA66_DETECT : out std_logic;
+ IDE_DDRQ : out std_logic;
+ IDE_CABLE_SELECT : out std_logic;
+ IDE_IO_WRITE : out std_logic;
+ IDE_IOC_HRDY : out std_logic;
+ IDE_DDACK : out std_logic;
+ IDE_CHIP_SELECT_1P : out std_logic;
+ IDE_CHIP_SELECT_3P : out std_logic;
+ IDE_IRQ : out std_logic;
+ IDE_ACTIVITY : out std_logic;
+ FPGA1 : out std_logic;
+ FPGA2 : out std_logic;
+ FPGA3 : out std_logic;
+ FPGA4 : out std_logic;
+ FPGA5 : out std_logic;
+ FPGA6 : out std_logic;
+ FPGA7 : out std_logic;
+ FPGA8 : out std_logic;
+ FPGA9 : out std_logic;
+ FPGA10 : out std_logic;
+ FPGA11 : out std_logic;
+ FPGA12 : out std_logic;
+ FPGA13 : out std_logic;
+ FPGA14 : out std_logic;
+ FPGA15 : out std_logic;
+ FPGA16 : out std_logic;
+ OUT1 : out std_logic;
+ OUT2 : out std_logic;
+ OUT3 : out std_logic;
+ OUT4 : out std_logic;
+ OUT5 : out std_logic;
+ OUT6 : out std_logic;
+ OUT7 : out std_logic;
+ OUT8 : out std_logic;
+ OUT9 : out std_logic;
+ OUT10 : out std_logic;
+ OUT11 : out std_logic;
+ OUT12 : out std_logic;
+ OUT13 : out std_logic;
+ OUT14 : out std_logic;
+ OUT15 : out std_logic;
+ OUT16 : out std_logic;
+ OUT17 : out std_logic;
+ OUT18 : out std_logic;
+ OUT19 : out std_logic;
+ OUT20 : out std_logic
+ );
+end ide;
+
+architecture Behavioral of ide is
+
+begin
+ LED_1 <= '1';
+ LED_2 <= '1';
+ LED_3 <= '1';
+ LED_4 <= '0';
+end Behavioral;
+
projects / raggedstone / commitdiff