#include <avr/io.h>
+#include <avr/interrupt.h>
#include <stdio.h>
#include "chassis.h"
#define _CDDR(port) __CDDR(port)
#define CDDR _CDDR(CHASSISPORT)
+static volatile int power_cnt = 0;
+static volatile int reset_cnt = 0;
+
static void chassis_set_pins(uint8_t pins, uint8_t state);
void chassis_init()
{
chassis_set_pins((1<<POWER_PIN) | (1<<RESET_PIN), 0);
CDDR |= ((1<<POWER_PIN) | (1<<RESET_PIN));
+
+ /* About 1ms */
+ OCR0 = ((F_CPU/256)/1000)-1;
+
+ TCCR0 = ((1<<WGM01) | (1<<CS02)); /* CTC, Prescaler 256 */
+ TIMSK |= (1<<OCIE0);
+
}
static void chassis_set_pins(uint8_t pins, uint8_t state)
static void chassis_power(int msec)
{
- volatile int i;
+ uint8_t old_SREG = SREG;
chassis_set_pins((1<<POWER_PIN), 1);
- /* FIXME */
- for(i = 0; i < (msec<<2); i++);
-
- chassis_set_pins((1<<POWER_PIN), 0);
+ cli();
+ if (!power_cnt)
+ power_cnt = msec;
+ SREG = old_SREG;
}
static void chassis_reset(int msec)
{
- volatile int i;
+ uint8_t old_SREG = SREG;
chassis_set_pins((1<<RESET_PIN), 1);
- /* FIXME */
- for(i = 0; i < (msec<<2); i++);
-
- chassis_set_pins((1<<RESET_PIN), 0);
+ cli();
+ if (!reset_cnt)
+ reset_cnt = msec;
+ SREG = old_SREG;
}
void chassis_control(unsigned char action)
break;
}
}
+
+ISR(TIMER0_COMP_vect)
+{
+ if (power_cnt) {
+ power_cnt--;
+
+ if (!power_cnt)
+ chassis_set_pins((1<<POWER_PIN), 0);
+ }
+ if (reset_cnt) {
+ reset_cnt--;
+
+ if (!reset_cnt)
+ chassis_set_pins((1<<RESET_PIN), 0);
+ }
+}