cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_clock.v

   1 //---------------------------------------------------------------------
   2 // FPGA MOONCRESTA   CLOCK GEN
   3 //
   4 // Version : 1.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 //---------------------------------------------------------------------
  15
  16
  17
  18 module mc_clock(
  19
  20 I_CLK_18M,
  21 O_CLK_12M,
  22 O_CLK_06M,
  23 O_CLK_06Mn
  24
  25 );
  26
  27 input  I_CLK_18M;
  28 output O_CLK_12M;
  29 output O_CLK_06M;
  30 output O_CLK_06Mn;
  31
  32 // 2/3 clock divider(duty 33%)
  33 reg [1:0] clk_ff1,clk_ff2;
  34 //I_CLK   1010101010101010101
  35 //c_ff10  0011110011110011110
  36 //c_ff11  0011000011000011000
  37 //c_ff20  0000110000110000110
  38 //c_ff21  0110000110000110000
  39 //O_12M   0000110110110110110
  40 always @(posedge I_CLK_18M)
  41 begin
  42    clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];
  43    clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];
  44    clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];
  45 end
  46 always @(negedge I_CLK_18M)
  47    clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];
  48
  49 // 2/3 clock         (duty 66%)
  50 assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];
  51
  52 // 1/3 clock divider (duty 50%)
  53 reg CLK_6M , CLK_6Mn;
  54 always @(posedge O_CLK_12M)
  55 begin
  56    CLK_6Mn <=  CLK_6M;
  57    CLK_6M  <= ~CLK_6M;
  58 end
  59 assign O_CLK_06M = CLK_6M;
  60 assign O_CLK_06Mn = CLK_6Mn;
  61
  62
  63 endmodule