]> cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/fpga.v
This version code now reads a TI tag properly.
[proxmark3-svn] / fpga / fpga.v
1 //-----------------------------------------------------------------------------
2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
3 // and the ARM. In the low-frequency modes it passes the data straight
4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
5 // frequency modes, the FPGA might perform some demodulation first, to
6 // reduce the amount of data that we must send to the ARM.
7 //
8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
9 // could be improved.
10 //
11 // Jonathan Westhues, March 2006
12 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
13 //-----------------------------------------------------------------------------
14
15 `include "lo_read.v"
16 `include "lo_passthru.v"
17 `include "lo_simulate.v"
18 `include "hi_read_tx.v"
19 `include "hi_read_rx_xcorr.v"
20 `include "hi_simulate.v"
21 `include "hi_iso14443a.v"
22 `include "util.v"
23
24 module fpga(
25 spcki, miso, mosi, ncs,
26 pck0i, ck_1356meg, ck_1356megb,
27 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
28 adc_d, adc_clk, adc_noe,
29 ssp_frame, ssp_din, ssp_dout, ssp_clk,
30 cross_hi, cross_lo,
31 dbg
32 );
33 input spcki, mosi, ncs;
34 output miso;
35 input pck0i, ck_1356meg, ck_1356megb;
36 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
37 input [7:0] adc_d;
38 output adc_clk, adc_noe;
39 input ssp_dout;
40 output ssp_frame, ssp_din, ssp_clk;
41 input cross_hi, cross_lo;
42 output dbg;
43
44 //assign pck0 = pck0i;
45 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
46 .O(pck0),
47 .I(pck0i)
48 );
49 //assign spck = spcki;
50 IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
51 .O(spck),
52 .I(spcki)
53 );
54 //-----------------------------------------------------------------------------
55 // The SPI receiver. This sets up the configuration word, which the rest of
56 // the logic looks at to determine how to connect the A/D and the coil
57 // drivers (i.e., which section gets it). Also assign some symbolic names
58 // to the configuration bits, for use below.
59 //-----------------------------------------------------------------------------
60
61 reg [15:0] shift_reg;
62 reg [7:0] divisor;
63 reg [7:0] conf_word;
64
65 // We switch modes between transmitting to the 13.56 MHz tag and receiving
66 // from it, which means that we must make sure that we can do so without
67 // glitching, or else we will glitch the transmitted carrier.
68 always @(posedge ncs)
69 begin
70 case(shift_reg[15:12])
71 4'b0001: conf_word <= shift_reg[7:0];
72 4'b0010: divisor <= shift_reg[7:0];
73 endcase
74 end
75
76 always @(posedge spck)
77 begin
78 if(~ncs)
79 begin
80 shift_reg[15:1] <= shift_reg[14:0];
81 shift_reg[0] <= mosi;
82 end
83 end
84
85 wire [2:0] major_mode;
86 assign major_mode = conf_word[7:5];
87
88 // For the low-frequency configuration:
89 wire lo_is_125khz;
90 assign lo_is_125khz = conf_word[3];
91
92 // For the high-frequency transmit configuration: modulation depth, either
93 // 100% (just quite driving antenna, steady LOW), or shallower (tri-state
94 // some fraction of the buffers)
95 wire hi_read_tx_shallow_modulation;
96 assign hi_read_tx_shallow_modulation = conf_word[0];
97
98 // For the high-frequency receive correlator: frequency against which to
99 // correlate.
100 wire hi_read_rx_xcorr_848;
101 assign hi_read_rx_xcorr_848 = conf_word[0];
102 // and whether to drive the coil (reader) or just short it (snooper)
103 wire hi_read_rx_xcorr_snoop;
104 assign hi_read_rx_xcorr_snoop = conf_word[1];
105
106 // For the high-frequency simulated tag: what kind of modulation to use.
107 wire [2:0] hi_simulate_mod_type;
108 assign hi_simulate_mod_type = conf_word[2:0];
109
110 //-----------------------------------------------------------------------------
111 // And then we instantiate the modules corresponding to each of the FPGA's
112 // major modes, and use muxes to connect the outputs of the active mode to
113 // the output pins.
114 //-----------------------------------------------------------------------------
115
116 lo_read lr(
117 pck0, ck_1356meg, ck_1356megb,
118 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
119 adc_d, lr_adc_clk,
120 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
121 cross_hi, cross_lo,
122 lr_dbg,
123 lo_is_125khz, divisor
124 );
125
126 lo_passthru lp(
127 pck0, ck_1356meg, ck_1356megb,
128 lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
129 adc_d, lp_adc_clk,
130 lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
131 cross_hi, cross_lo,
132 lp_dbg, divisor
133 );
134
135 lo_simulate ls(
136 pck0, ck_1356meg, ck_1356megb,
137 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
138 adc_d, ls_adc_clk,
139 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
140 cross_hi, cross_lo,
141 ls_dbg
142 );
143
144 hi_read_tx ht(
145 pck0, ck_1356meg, ck_1356megb,
146 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
147 adc_d, ht_adc_clk,
148 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
149 cross_hi, cross_lo,
150 ht_dbg,
151 hi_read_tx_shallow_modulation
152 );
153
154 hi_read_rx_xcorr hrxc(
155 pck0, ck_1356meg, ck_1356megb,
156 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
157 adc_d, hrxc_adc_clk,
158 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
159 cross_hi, cross_lo,
160 hrxc_dbg,
161 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
162 );
163
164 hi_simulate hs(
165 pck0, ck_1356meg, ck_1356megb,
166 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
167 adc_d, hs_adc_clk,
168 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
169 cross_hi, cross_lo,
170 hs_dbg,
171 hi_simulate_mod_type
172 );
173
174 hi_iso14443a hisn(
175 pck0, ck_1356meg, ck_1356megb,
176 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
177 adc_d, hisn_adc_clk,
178 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
179 cross_hi, cross_lo,
180 hisn_dbg,
181 hi_simulate_mod_type
182 );
183
184 // Major modes:
185 // 000 -- LF reader (generic)
186 // 001 -- LF simulated tag (generic)
187 // 010 -- HF reader, transmitting to tag; modulation depth selectable
188 // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
189 // 100 -- HF simulated tag
190 // 101 -- HF ISO14443-A
191 // 110 -- LF passthrough
192 // 111 -- everything off
193
194 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
195 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
196 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
197 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
198 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
199 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
200 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
201 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
202 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
203 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
204 mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
205
206 // In all modes, let the ADC's outputs be enabled.
207 assign adc_noe = 1'b0;
208
209 endmodule
Impressum, Datenschutz