DoAcquisition125k(at134khz);
}
-//-----------------------------------------------------------------------------
-// Read a TI-type tag. We assume that the tag has already been illuminated,
-// and that the exciting signal has been turned off. That means that we just
-// acquire the `one-bit DAC' bits from the comparator.
-//-----------------------------------------------------------------------------
void AcquireTiType(void)
{
int i;
- int n = sizeof(BigBuf);
+ int n = 5000;
// clear buffer
memset(BigBuf,0,sizeof(BigBuf));
- // Set up the synchronous serial port
+ // Set up the synchronous serial port
PIO_DISABLE = (1<<GPIO_SSC_DIN);
PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);
+ // steal this pin from the SSP and use it to control the modulation
+ PIO_ENABLE = (1<<GPIO_SSC_DOUT);
+ PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);
+
SSC_CONTROL = SSC_CONTROL_RESET;
SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
SSC_CLOCK_DIVISOR = 12;
SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
- SSC_TRANSMIT_CLOCK_MODE = 0;
- SSC_TRANSMIT_FRAME_MODE = 0;
-
- i = 0;
- for(;;) {
- if(SSC_STATUS & SSC_STATUS_RX_READY) {
- BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer
- i++; if(i >= n) return;
- }
- WDT_HIT();
- }
-}
+ SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
+ SSC_TRANSMIT_CLOCK_MODE = 0;
+ SSC_TRANSMIT_FRAME_MODE = 0;
-void AcquireRawBitsTI(void)
-{
LED_D_ON();
- // TI tags charge at 134.2Khz
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+
+ // modulate antenna
+ PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
// Charge TI tag for 50ms.
SpinDelay(50);
+
+ // stop modulating antenna and listen
+ PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
+
LED_D_OFF();
- LED_A_ON();
- // Place FPGA in passthrough mode so as to stop driving the LF coil,
- // in this mode the CROSS_LO line connects to SSP_DIN
+ i = 0;
+ for(;;) {
+ if(SSC_STATUS & SSC_STATUS_RX_READY) {
+ BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer
+ i++; if(i >= n) return;
+ }
+ WDT_HIT();
+ }
+
+ // return stolen pin ro SSP
+ PIO_DISABLE = (1<<GPIO_SSC_DOUT);
+ PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);
+}
+
+void AcquireRawBitsTI(void)
+{
+ LED_D_ON();
+ // TI tags charge at 134.2Khz
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
+ // Place FPGA in passthrough mode, in this mode the CROSS_LO line
+ // connects to SSP_DIN and the SSP_DOUT logic level controls
+ // whether we're modulating the antenna (high)
+ // or listening to the antenna (low)
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
// get TI tag data into the buffer
AcquireTiType();
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- LED_A_OFF();
}
//-----------------------------------------------------------------------------
adc_d, adc_clk,\r
ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
cross_hi, cross_lo,\r
- dbg\r
+ dbg, divisor\r
);\r
input pck0, ck_1356meg, ck_1356megb;\r
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
output ssp_frame, ssp_din, ssp_clk;\r
input cross_hi, cross_lo;\r
output dbg;\r
+ input [7:0] divisor;\r
\r
-// No logic, straight through.\r
+reg [7:0] pck_divider;\r
+reg ant_lo;\r
\r
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
+// which is high for (divisor+1) pck0 cycles and low for the same duration\r
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
+always @(posedge pck0)\r
+begin\r
+ if(pck_divider == divisor[7:0])\r
+ begin\r
+ pck_divider <= 8'd0;\r
+ ant_lo = !ant_lo;\r
+ end\r
+ else\r
+ begin\r
+ pck_divider <= pck_divider + 1;\r
+ end\r
+end\r
+\r
+// the antenna is modulated when ssp_dout = 1, when 0 the\r
+// antenna drivers stop modulating and go into listen mode\r
assign pwr_oe3 = 1'b0;\r
-assign pwr_oe1 = 1'b1;\r
-assign pwr_oe2 = 1'b1;\r
-assign pwr_oe4 = 1'b1;\r
-assign pwr_lo = 1'b0;\r
+assign pwr_oe1 = ssp_dout;\r
+assign pwr_oe2 = ssp_dout;\r
+assign pwr_oe4 = ssp_dout;\r
+assign pwr_lo = ant_lo && ssp_dout;\r
assign pwr_hi = 1'b0;\r
assign adc_clk = 1'b0;\r
assign ssp_din = cross_lo;\r
projects / proxmark3-svn / commitdiff