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[raggedstone] / heartbeat / source / pcipargen.vhd

--+-------------------------------------------------------------------------------------------------+\r
--|																									|\r
--|  File:		pcipargen.vhd	                                                          			|\r
--|																									|\r
--|  Project:		pci32tlite_oc																	|\r
--|																									|\r
--|  Description: 	PCI Parity Generator.															|\r
--|					PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD,	|\r
--|					CBE and PAR is even.                                      						|\r
--|	 																								|\r
--+-------------------------------------------------------------------------------------------------+\r
--|																									|\r
--|  Revision history :																				|\r
--|  Date 		  Version	Author	Description														|\r
--|  2005-05-13   R00A00	PAU		First alfa revision	(eng)										|\r
--|																									|\r
--|  To do:		 																					|\r
--|																									|\r
--+-------------------------------------------------------------------------------------------------+\r
--+-----------------------------------------------------------------+\r
--| 																|\r
--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org   		| \r
--| 																|\r
--|  This source file may be used and distributed without     		|\r
--|  restriction provided that this copyright statement is not		|\r
--|  removed from the file and that any derivative work contains	|\r
--|  the original copyright notice and the associated disclaimer.	|\r
--|                                                              	|\r
--|  This source file is free software; you can redistribute it     |\r
--|  and/or modify it under the terms of the GNU Lesser General     |\r
--|  Public License as published by the Free Software Foundation;   |\r
--|  either version 2.1 of the License, or (at your option) any     |\r
--|  later version.                                                 |\r
--| 																|\r
--|  This source is distributed in the hope that it will be         |\r
--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
--|  details.                                                       |\r
--| 																|\r
--|  You should have received a copy of the GNU Lesser General      |\r
--|  Public License along with this source; if not, download it     |\r
--|  from http://www.opencores.org/lgpl.shtml                       |\r
--| 																|\r
--+-----------------------------------------------------------------+ \r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									LIBRARIES									|\r
--+-----------------------------------------------------------------------------+\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
\r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									ENTITY   									|\r
--+-----------------------------------------------------------------------------+\r
\r
entity pcipargen is\r
port (\r
\r
	clk_i			: in std_logic;\r
	pcidatout_i		: in std_logic_vector(31 downto 0);\r
	cbe_i			: in std_logic_vector(3 downto 0);\r
	parOE_i	  		: in std_logic;\r
	par_o			: out std_logic\r
	\r
);   \r
end pcipargen;\r
\r
\r
architecture rtl of pcipargen is\r
\r
\r
--+-----------------------------------------------------------------------------+\r
--|									COMPONENTS									|\r
--+-----------------------------------------------------------------------------+\r
--+-----------------------------------------------------------------------------+\r
--|									CONSTANTS  									|\r
--+-----------------------------------------------------------------------------+\r
--+-----------------------------------------------------------------------------+\r
--|									SIGNALS   									|\r
--+-----------------------------------------------------------------------------+\r
\r
  	signal d			: std_logic_vector(31 downto 0);\r
  	signal pardat		: std_logic;\r
  	signal parcbe		: std_logic;\r
  	signal par			: std_logic;\r
  	signal par_s		: std_logic;\r
\r
component sync\r
port (\r
    clk             : in std_logic;\r
    d           : in std_logic;\r
    q               : out std_logic\r
);\r
end component;\r
\r
component sync2\r
port (\r
    clk             : in std_logic;\r
    d           : in std_logic;\r
    q               : out std_logic\r
);\r
end component;\r
\r
begin\r
\r
\r
	d <= pcidatout_i;\r
\r
	\r
    --+-------------------------------------------------------------------------+\r
	--|  building parity														|\r
    --+-------------------------------------------------------------------------+\r
	\r
	pardat 	<= d(0)  xor d(1)  xor d(2)  xor d(3)  xor d(4)  xor d(5)  xor d(6)  xor d(7)  xor \r
			   d(8)  xor d(9)  xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor \r
			   d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor \r
			   d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);\r
						\r
	parcbe 	<= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3); \r
	\r
	par <= pardat xor parcbe;\r
\r
    -- u1: sync port map ( clk => clk_i, d => par, q => par_s );\r
	\r
    u1: sync2 port map (\r
		clk => clk_i,\r
		d => par,\r
		q => par_s\r
	);\r
	\r
\r
    --+-------------------------------------------------------------------------+\r
    --|  PAR																	|\r
    --+-------------------------------------------------------------------------+\r
\r
	par_o <= par_s when ( parOE_i = '1' ) else 'Z';\r
\r
\r
end rtl;\r