cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/INTERRUPT.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: INTERRUPT.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all;
   8
   9 entity INTERRUPT is
  10         port
  11         (
  12         PCI_CLOCK               :in             std_logic;
  13         PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)
  14         RESET                           :in     std_logic;
  15         TAST_SETn               :in     std_logic;
  16         TAST_RESn               :in     std_logic;
  17         INT_IN_0                :in             std_logic;
  18         INT_IN_1                :in             std_logic;
  19         INT_IN_2                :in             std_logic;
  20         INT_IN_3                :in             std_logic;
  21         INT_IN_4                :in             std_logic;
  22         INT_IN_5                :in             std_logic;
  23         INT_IN_6                :in             std_logic;
  24         INT_IN_7                :in             std_logic;
  25         TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)
  26         READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register
  27         INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts
  28         INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register
  29         INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register
  30         INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer
  31         PCI_INTAn               :out    std_logic               -- PCI interrupt line
  32         );
  33
  34 end entity INTERRUPT;
  35
  36 architecture INTERRUPT_DESIGN of INTERRUPT is
  37
  38         signal  SIG_TAST_Q              :std_logic;
  39         signal  SIG_TAST_Qn             :std_logic;
  40
  41
  42         signal  SIG_INTA                        :std_logic;
  43
  44         signal FF_A                     :std_logic_vector(7 downto 0);
  45         signal FF_B                     :std_logic_vector(7 downto 0);
  46         signal SET                      :std_logic_vector(7 downto 0);
  47
  48         signal  SIG_PROPAGATE_INT :std_logic;
  49         signal  SIG_PROPAGATE_INT_SECOND :std_logic;
  50         signal  REG :std_logic_vector(7 downto 0);
  51
  52 begin
  53
  54
  55
  56
  57 ------------------------------------------------------
  58         process (PCI_CLOCK)
  59         begin
  60                 if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then
  61
  62                         SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);
  63
  64                         SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);
  65
  66                 end if;
  67         end process;
  68
  69 ------------------------------------------------------
  70
  71         process (PCI_CLOCK)
  72         begin
  73     if (PCI_RSTn = '0') then
  74                                         SET <= "00000000";
  75           FF_A  <= "00000000";
  76           FF_B  <= "00000000";
  77
  78                 elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
  79                 if(RESET = '1') then
  80                                                 SET <= "00000000";
  81             FF_A        <= "00000000";
  82             FF_B        <= "00000000";
  83       else
  84
  85                         FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag
  86
  87                         FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full
  88                         FF_A(2) <=                      INT_IN_2 ;
  89                         FF_A(3) <=                      INT_IN_3 ;
  90
  91                         FF_A(4) <=                      INT_IN_4 ;
  92
  93                         FF_A(5) <=                      INT_IN_5 ;
  94                         FF_A(6) <=                      INT_IN_6 ;
  95                         FF_A(7) <=                      INT_IN_7 ;
  96
  97                         FF_B    <= FF_A ;
  98
  99                         SET <= FF_A AND not FF_B;
 100                 end if;
 101                 end if;
 102         end process;
 103
 104         process (PCI_CLOCK,PCI_RSTn)
 105         begin
 106                 if (PCI_RSTn = '0') then
 107                         REG <= "00000000";
 108
 109                 elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
 110                                 if(RESET = '1') then
 111                                         REG <= "00000000";
 112
 113                 elsif(SIG_TAST_Q = '1') then
 114                         REG <= "00000000" or SET;
 115
 116         elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
 117             REG <= (REG AND NOT INT_RES) OR SET;
 118         else
 119             REG <= REG OR SET;
 120         end if;
 121     end if;
 122         end process;
 123
 124         SIG_PROPAGATE_INT <= SIG_TAST_Q
 125             OR (REG(0) AND INT_MASKE(0))
 126             OR (REG(1) AND INT_MASKE(1))
 127             OR (REG(2) AND INT_MASKE(2))
 128             OR (REG(3) AND INT_MASKE(3))
 129             OR (REG(4) AND INT_MASKE(4))
 130             OR (REG(5) AND INT_MASKE(5))
 131             OR (REG(6) AND INT_MASKE(6))
 132             OR (REG(7) AND INT_MASKE(7));
 133
 134         process (PCI_CLOCK)
 135         begin
 136                 if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then
 137         SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;
 138     end if;
 139   end process;
 140
 141
 142           INTAn <= not SIG_PROPAGATE_INT_SECOND;
 143         PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';
 144
 145         INT_REG <= REG;
 146
 147 end architecture INTERRUPT_DESIGN;