cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/pcidec.v

   1 //  Copyright (C) 2005 Peio Azkarate, peio@opencores.org
   2 //  Copyright (C) 2006 Jeff Carr, jcarr@opencores.org
   3 //      Copyleft GPL v2
   4
   5 module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i,
   6         pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o);
   7
   8         // General
   9         input clk_i;
  10         input nrst_i;
  11         // pci
  12         input [31:0] ad_i;
  13         input [3:0] cbe_i;
  14         input idsel_i;
  15         // control
  16         input [31:25] bar0_i;
  17         input memEN_i;
  18         input pciadrLD_i;
  19         output adrcfg_o;
  20         output adrmem_o;
  21         output [24:1] adr_o;
  22         output [3:0] cmd_o;
  23
  24         reg [31:0] adr;
  25         reg [3:0] cmd;
  26         reg idsel_s;
  27         wire a1;
  28
  29         //+-------------------------------------------------------------------------+
  30         //|  Load PCI Signals                                                                                                           |
  31         //+-------------------------------------------------------------------------+
  32
  33         always @( negedge nrst_i or posedge clk_i )
  34         begin
  35                 if( nrst_i == 0 )
  36                 begin
  37                         adr <= 23'b1111_1111_1111_1111_1111_111;
  38                         cmd <= 3'b111;
  39                         idsel_s <= 1'b0;
  40                 end
  41                 else
  42                         if ( pciadrLD_i == 1 )
  43                         begin
  44                                 adr <= ad_i;
  45                                 cmd <= cbe_i;
  46                                 idsel_s <= idsel_i;
  47                         end
  48         end
  49
  50         assign adrmem_o = (
  51                 ( memEN_i == 1'b1 ) &&
  52                 ( adr [31:25] == bar0_i ) &&
  53                 ( adr [1:0] == 2'b00 ) &&
  54                 ( cmd [3:1] == 3'b011 )
  55         ) ? 1'b1 : 1'b0;
  56
  57         assign adrcfg_o = (
  58                 ( idsel_s == 1'b1 ) &&
  59                 ( adr [1:0] == 2'b00 ) &&
  60                 ( cmd [3:1] == 3'b101 )
  61         ) ? 1'b1 : 1'b0;
  62
  63         assign a1 = ~ ( cbe_i [3] && cbe_i [2] );
  64         assign adr_o = {adr [24:2], a1};
  65         assign cmd_o = cmd;
  66
  67 endmodule