cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/pcidmux.v

   1 // Copyright (C) 2005 Peio Azkarate, peio@opencores.org
   2 // Copyright (C) 2006 Jeff Carr, jcarr@opencores.org
   3 //
   4 // I think what this does is handle 16 vs 32 bit pci accesses
   5
   6 module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i,
   7         wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o);
   8
   9         input clk_i;
  10         input nrst_i;
  11
  12         // d_io                 : inout std_logic_vector(31 downto 0);
  13         inout [31:0] d_io;
  14         output [31:0] pcidatout_o;
  15
  16         input pcidOE_i;
  17         input wbdatLD_i;
  18         input wbrgdMX_i;
  19         input wbd16MX_i;
  20
  21         input [15:0] wb_dat_i;
  22         output [15:0] wb_dat_o;
  23         input [31:0] rg_dat_i;
  24         output [31:0] rg_dat_o;
  25
  26         wire [31:0] pcidatin;
  27         wire [31:0] pcidatout;
  28
  29         reg [15:0] wb_dat_is;
  30
  31         // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i)
  32         always @(negedge nrst_i or posedge clk_i)
  33         begin
  34                 if ( nrst_i == 0 )
  35                         wb_dat_is <= 16'b1111_1111_1111_1111;
  36                 else
  37                         if ( wbdatLD_i == 1 )
  38                                 wb_dat_is <= wb_dat_i;
  39         end
  40
  41         assign pcidatin = d_io;
  42         assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ;
  43
  44         assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [31:24];
  45         assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16];
  46         assign pcidatout [15:8]  = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [15:8];
  47         assign pcidatout [7:0]   = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0];
  48
  49         assign pcidatout_o = pcidatout;
  50         assign rg_dat_o = pcidatin;
  51
  52         assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0];
  53         assign wb_dat_o [7:0]  = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8];
  54
  55 endmodule