cvs.zerfleddert.de Git - raggedstone/blob - ideboard/source/ide.vhd

   1 ----------------------------------------------------------------------------------
   2 -- Company:
   3 -- Engineer:
   4 --
   5 -- Create Date:    22:50:29 03/05/2007
   6 -- Design Name:
   7 -- Module Name:    ide - Behavioral
   8 -- Project Name:
   9 -- Target Devices:
  10 -- Tool versions:
  11 -- Description:
  12 --
  13 -- Dependencies:
  14 --
  15 -- Revision:
  16 -- Revision 0.01 - File Created
  17 -- Additional Comments:
  18 --
  19 ----------------------------------------------------------------------------------
  20 library IEEE;
  21 use IEEE.STD_LOGIC_1164.ALL;
  22 use IEEE.STD_LOGIC_ARITH.ALL;
  23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
  24
  25 ---- Uncomment the following library declaration if instantiating
  26 ---- any Xilinx primitives in this code.
  27 --library UNISIM;
  28 --use UNISIM.VComponents.all;
  29
  30 entity ide is
  31     Port ( LED_1 : out  STD_LOGIC;
  32            LED_2 : out  STD_LOGIC;
  33            LED_3 : out  STD_LOGIC;
  34            LED_4 : out  STD_LOGIC;
  35            IDE_DATA : out std_logic_vector(15 downto 0);
  36            IDE_ADDR : out std_logic_vector(2 downto 0);
  37            IDE_RESET : out std_logic;
  38            IDE_IO_READ : out std_logic;
  39            IDE_GPIO_DMA66_DETECT : out std_logic;
  40            IDE_DDRQ : out std_logic;
  41            IDE_CABLE_SELECT : out std_logic;
  42            IDE_IO_WRITE : out std_logic;
  43            IDE_IOC_HRDY : out std_logic;
  44            IDE_DDACK : out std_logic;
  45            IDE_CHIP_SELECT_1P : out std_logic;
  46            IDE_CHIP_SELECT_3P : out std_logic;
  47            IDE_IRQ : out std_logic;
  48            IDE_ACTIVITY : out std_logic;
  49            FPGA1 : in std_logic;
  50            FPGA2 : in std_logic;
  51            FPGA3 : in std_logic;
  52            FPGA4 : in std_logic;
  53            FPGA5 : out std_logic;
  54            FPGA6 : out std_logic;
  55            FPGA7 : out std_logic;
  56            FPGA8 : out std_logic;
  57            FPGA9 : out std_logic;
  58            FPGA10 : out std_logic;
  59            FPGA11 : out std_logic;
  60            FPGA12 : out std_logic;
  61            FPGA13 : out std_logic;
  62            FPGA14 : out std_logic;
  63            FPGA15 : out std_logic;
  64            FPGA16 : out std_logic;
  65            OUT1 : out std_logic;
  66            OUT2 : out std_logic;
  67            OUT3 : out std_logic;
  68            OUT4 : out std_logic;
  69            OUT5 : out std_logic;
  70            OUT6 : out std_logic;
  71            OUT7 : out std_logic;
  72            OUT8 : out std_logic;
  73            OUT9 : out std_logic;
  74            OUT10 : out std_logic;
  75            OUT11 : out std_logic;
  76            OUT12 : out std_logic;
  77            OUT13 : out std_logic;
  78            OUT14 : out std_logic;
  79            OUT15 : out std_logic;
  80            OUT16 : out std_logic;
  81            OUT17 : out std_logic;
  82            OUT18 : out std_logic;
  83            OUT19 : out std_logic;
  84            OUT20 : out std_logic
  85            );
  86 end ide;
  87
  88 architecture Behavioral of ide is
  89
  90 begin
  91         LED_1 <= FPGA1;
  92         LED_2 <= FPGA2;
  93         LED_3 <= FPGA3;
  94         LED_4 <= FPGA4;
  95 end Behavioral;
  96