cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/top.vhd

   1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
   2
   3
   4
   5 LIBRARY ieee;
   6
   7 USE ieee.std_logic_1164.ALL;
   8 USE ieee.numeric_std.ALL;
   9
  10
  11 entity dhwk is
  12       Port ( KONST_1 : In    std_logic;
  13              PCI_CBEn : In    std_logic_vector (3 downto 0);
  14              PCI_CLOCK : In    std_logic;
  15              PCI_FRAMEn : In    std_logic;
  16              PCI_IDSEL : In    std_logic;
  17              PCI_IRDYn : In    std_logic;
  18              PCI_RSTn : In    std_logic;
  19              SERIAL_IN : In    std_logic;
  20              SPC_RDY_IN : In    std_logic;
  21              TAST_RESn : In    std_logic;
  22              TAST_SETn : In    std_logic;
  23               PCI_AD : InOut std_logic_vector (31 downto 0);
  24              PCI_PAR : InOut std_logic;
  25              PCI_DEVSELn : Out   std_logic;
  26              PCI_INTAn : Out   std_logic;
  27              PCI_PERRn : Out   std_logic;
  28              PCI_SERRn : Out   std_logic;
  29              PCI_STOPn : Out   std_logic;
  30              PCI_TRDYn : Out   std_logic;
  31              SERIAL_OUT : Out   std_logic;
  32              SPC_RDY_OUT : Out   std_logic;
  33              TB_IDSEL : Out   std_logic;
  34              TB_nDEVSEL : Out   std_logic;
  35              TB_nINTA : Out   std_logic );
  36 end dhwk;
  37
  38 architecture SCHEMATIC of dhwk is
  39
  40    SIGNAL gnd : std_logic := '0';
  41    SIGNAL vcc : std_logic := '1';
  42
  43    signal READ_XX7_6 : std_logic;
  44    signal  RESERVE : std_logic;
  45    signal SR_ERROR : std_logic;
  46    signal  R_ERROR : std_logic;
  47    signal  S_ERROR : std_logic;
  48    signal WRITE_XX3_2 : std_logic;
  49    signal WRITE_XX5_4 : std_logic;
  50    signal WRITE_XX7_6 : std_logic;
  51    signal READ_XX1_0 : std_logic;
  52    signal READ_XX3_2 : std_logic;
  53    signal    INTAn : std_logic;
  54    signal    TRDYn : std_logic;
  55    signal READ_XX5_4 : std_logic;
  56    signal  DEVSELn : std_logic;
  57    signal FIFO_RDn : std_logic;
  58    signal WRITE_XX1_0 : std_logic;
  59    signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
  60    signal SYNC_FLAG : std_logic_vector (7 downto 0);
  61    signal  INT_REG : std_logic_vector (7 downto 0);
  62    signal REVISON_ID : std_logic_vector (7 downto 0);
  63    signal VENDOR_ID : std_logic_vector (15 downto 0);
  64    signal READ_SEL : std_logic_vector (1 downto 0);
  65    signal   AD_REG : std_logic_vector (31 downto 0);
  66    signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
  67    signal R_EFn : std_logic;
  68    signal R_FFn : std_logic;
  69    signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
  70    signal R_HFn : std_logic;
  71    signal S_EFn : std_logic;
  72    signal S_FFn : std_logic;
  73    signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
  74    signal S_HFn : std_logic;
  75    signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
  76    signal R_FIFO_READn : std_logic;
  77    signal R_FIFO_RESETn : std_logic;
  78    signal R_FIFO_RTn : std_logic;
  79    signal R_FIFO_WRITEn : std_logic;
  80    signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
  81    signal S_FIFO_READn : std_logic;
  82    signal S_FIFO_RESETn : std_logic;
  83    signal S_FIFO_RTn : std_logic;
  84    signal S_FIFO_WRITEn : std_logic;
  85
  86    component MESS_1_TB
  87       Port ( DEVSELn : In    std_logic;
  88                INTAn : In    std_logic;
  89              KONST_1 : In    std_logic;
  90              PCI_IDSEL : In    std_logic;
  91              REG_OUT_XX7 : In    std_logic_vector (7 downto 0);
  92              TB_DEVSELn : Out   std_logic;
  93              TB_INTAn : Out   std_logic;
  94              TB_PCI_IDSEL : Out   std_logic );
  95    end component;
  96
  97    component VEN_REV_ID
  98       Port (  REV_ID : Out   std_logic_vector (7 downto 0);
  99               VEN_ID : Out   std_logic_vector (15 downto 0) );
 100    end component;
 101
 102    component INTERRUPT
 103       Port ( INT_IN_0 : In    std_logic;
 104              INT_IN_1 : In    std_logic;
 105              INT_IN_2 : In    std_logic;
 106              INT_IN_3 : In    std_logic;
 107              INT_IN_4 : In    std_logic;
 108              INT_IN_5 : In    std_logic;
 109              INT_IN_6 : In    std_logic;
 110              INT_IN_7 : In    std_logic;
 111              INT_MASKE : In    std_logic_vector (7 downto 0);
 112              INT_RES : In    std_logic_vector (7 downto 0);
 113              PCI_CLOCK : In    std_logic;
 114              PCI_RSTn : In    std_logic;
 115              READ_XX5_4 : In    std_logic;
 116                RESET : In    std_logic;
 117              TAST_RESn : In    std_logic;
 118              TAST_SETn : In    std_logic;
 119                TRDYn : In    std_logic;
 120              INT_REG : Out   std_logic_vector (7 downto 0);
 121                INTAn : Out   std_logic;
 122              PCI_INTAn : Out   std_logic );
 123    end component;
 124
 125    component FIFO_CONTROL
 126       Port ( FIFO_RDn : In    std_logic;
 127              FLAG_IN_0 : In    std_logic;
 128              FLAG_IN_4 : In    std_logic;
 129                 HOLD : In    std_logic;
 130              KONST_1 : In    std_logic;
 131              PCI_CLOCK : In    std_logic;
 132              PSC_ENABLE : In    std_logic;
 133                R_EFn : In    std_logic;
 134                R_FFn : In    std_logic;
 135                R_HFn : In    std_logic;
 136                RESET : In    std_logic;
 137                S_EFn : In    std_logic;
 138                S_FFn : In    std_logic;
 139              S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
 140                S_HFn : In    std_logic;
 141              SERIAL_IN : In    std_logic;
 142              SPC_ENABLE : In    std_logic;
 143              SPC_RDY_IN : In    std_logic;
 144              WRITE_XX1_0 : In    std_logic;
 145              R_ERROR : Out   std_logic;
 146              R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
 147              R_FIFO_READn : Out   std_logic;
 148              R_FIFO_RESETn : Out   std_logic;
 149              R_FIFO_RETRANSMITn : Out   std_logic;
 150              R_FIFO_WRITEn : Out   std_logic;
 151              RESERVE : Out   std_logic;
 152              S_ERROR : Out   std_logic;
 153              S_FIFO_READn : Out   std_logic;
 154              S_FIFO_RESETn : Out   std_logic;
 155              S_FIFO_RETRANSMITn : Out   std_logic;
 156              S_FIFO_WRITEn : Out   std_logic;
 157              SERIAL_OUT : Out   std_logic;
 158              SPC_RDY_OUT : Out   std_logic;
 159              SR_ERROR : Out   std_logic;
 160              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
 161    end component;
 162
 163    component PCI_TOP
 164       Port (    FLAG : In    std_logic_vector (7 downto 0);
 165              INT_REG : In    std_logic_vector (7 downto 0);
 166              PCI_CBEn : In    std_logic_vector (3 downto 0);
 167              PCI_CLOCK : In    std_logic;
 168              PCI_FRAMEn : In    std_logic;
 169              PCI_IDSEL : In    std_logic;
 170              PCI_IRDYn : In    std_logic;
 171              PCI_RSTn : In    std_logic;
 172              R_FIFO_Q : In    std_logic_vector (7 downto 0);
 173              REVISON_ID : In    std_logic_vector (7 downto 0);
 174              VENDOR_ID : In    std_logic_vector (15 downto 0);
 175               PCI_AD : InOut std_logic_vector (31 downto 0);
 176              PCI_PAR : InOut std_logic;
 177               AD_REG : Out   std_logic_vector (31 downto 0);
 178              DEVSELn : Out   std_logic;
 179              FIFO_RDn : Out   std_logic;
 180              PCI_DEVSELn : Out   std_logic;
 181              PCI_PERRn : Out   std_logic;
 182              PCI_SERRn : Out   std_logic;
 183              PCI_STOPn : Out   std_logic;
 184              PCI_TRDYn : Out   std_logic;
 185              READ_SEL : Out   std_logic_vector (1 downto 0);
 186              READ_XX1_0 : Out   std_logic;
 187              READ_XX3_2 : Out   std_logic;
 188              READ_XX5_4 : Out   std_logic;
 189              READ_XX7_6 : Out   std_logic;
 190              REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
 191              REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
 192              REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
 193                TRDYn : Out   std_logic;
 194              WRITE_XX1_0 : Out   std_logic;
 195              WRITE_XX3_2 : Out   std_logic;
 196              WRITE_XX5_4 : Out   std_logic;
 197              WRITE_XX7_6 : Out   std_logic );
 198    end component;
 199
 200 component fifo_generator_v3_2
 201         port (
 202         clk: IN std_logic;
 203         din: IN std_logic_VECTOR(7 downto 0);
 204         rd_en: IN std_logic;
 205         rst: IN std_logic;
 206         wr_en: IN std_logic;
 207         almost_empty: OUT std_logic;
 208         almost_full: OUT std_logic;
 209         dout: OUT std_logic_VECTOR(7 downto 0);
 210         empty: OUT std_logic;
 211         full: OUT std_logic;
 212         prog_full: OUT std_logic);
 213 end component;
 214
 215 begin
 216
 217    I19 : MESS_1_TB
 218       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
 219                  PCI_IDSEL=>PCI_IDSEL,
 220                  REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
 221                  TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
 222                  TB_PCI_IDSEL=>TB_IDSEL );
 223    I18 : VEN_REV_ID
 224       Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
 225                  VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
 226    I16 : INTERRUPT
 227       Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
 228                  INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
 229                  INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
 230                  INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
 231                  INT_RES(7 downto 0)=>AD_REG(7 downto 0),
 232                  PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
 233                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
 234                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
 235                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
 236                  INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
 237    I14 : FIFO_CONTROL
 238       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
 239                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
 240                  PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
 241                  R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
 242                  RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
 243                  S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
 244                  S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
 245                  SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
 246                  WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
 247                  R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
 248                  R_FIFO_READn=>R_FIFO_READn,
 249                  R_FIFO_RESETn=>R_FIFO_RESETn,
 250                  R_FIFO_RETRANSMITn=>R_FIFO_RTn,
 251                  R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
 252                  S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
 253                  S_FIFO_RESETn=>S_FIFO_RESETn,
 254                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,
 255                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
 256                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
 257                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
 258    I1 : PCI_TOP
 259       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
 260                  INT_REG(7 downto 0)=>INT_REG(7 downto 0),
 261                  PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
 262                  PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
 263                  PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
 264                  PCI_RSTn=>PCI_RSTn,
 265                  R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
 266                  REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
 267                  VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
 268                  PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
 269                  PCI_PAR=>PCI_PAR,
 270                  AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 271                  DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
 272                  PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
 273                  PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
 274                  PCI_TRDYn=>PCI_TRDYn,
 275                  READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
 276                  READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
 277                  READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
 278                  REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
 279                  REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
 280                  REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
 281                  TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
 282                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
 283                  WRITE_XX7_6=>WRITE_XX7_6 );
 284
 285 receive_fifo : fifo_generator_v3_2
 286                 port map (
 287                         clk => PCI_CLOCK,
 288                         din => R_FIFO_D_IN,
 289                         rd_en => not R_FIFO_READn,
 290                         rst => not R_FIFO_RESETn,
 291                         wr_en => not R_FIFO_WRITEn,
 292                         dout => R_FIFO_Q_OUT,
 293                         empty => R_EFn,
 294                         full => R_FFn,
 295                         prog_full => R_HFn);
 296
 297 send_fifo : fifo_generator_v3_2
 298                 port map (
 299                         clk => PCI_CLOCK,
 300                         din => S_FIFO_D_IN,
 301                         rd_en => not S_FIFO_READn,
 302                         rst => not S_FIFO_RESETn,
 303                         wr_en => not S_FIFO_WRITEn,
 304                         dout => S_FIFO_Q_OUT,
 305                         empty => S_EFn,
 306                         full => S_FFn,
 307                         prog_full => S_HFn);
 308 end SCHEMATIC;