add PCI_nREQ

diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 57b59c49c5c55afa7d2346375a8cccc1716c329a..1924315cfc24e35f46406366b647fe3d82bdc31c 100644 (file)
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -48,6 +48,7 @@ NET "PCI_nSERR"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nREQ"  LOC = "C18" | IOSTANDARD = PCI33_3 ;
 NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
 NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
 NET "IDE1"  LOC = "Y1" | IOSTANDARD = LVCMOS33 ;

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index c7982941f1283337f185315ab2d796ae4ec64273..3d369cf5dae28104afb9dd4d3cf51a7dc1c2cd01 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -44,6 +44,7 @@ port (
     -- General \r
     PCI_CLK     : in std_logic;\r
     PCI_nRES    : in std_logic;\r
+    PCI_nREQ    : out std_logic;\r
     \r
     -- PCI target 32bits\r
     PCI_AD      : inout std_logic_vector(31 downto 0);\r
@@ -161,6 +162,8 @@ end component;
 \r
 begin\r
 \r
+       PCI_nREQ <= '1';\r
+\r
 --+-----------------------------------------+\r
 --|  PCI Target                                                        |\r
 --+-----------------------------------------+\r