give LED's more sensible names

blink more ;-)

diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 31d028c5174f916438f2bdc5d6798fa10af2fee2..9f9ac54fe32baab9276af50efa887b64272e4361 100644 (file)
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -1,5 +1,5 @@
-NET "LED_ACCESS"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
-NET "LED_INIT"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
+NET "LED2"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
+NET "LED3"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;

 NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<10>"  LOC = "E9" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<11>"  LOC = "F11" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<10>"  LOC = "E9" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<11>"  LOC = "F11" | IOSTANDARD = PCI33_3 ;


@@ -48,4 +48,5 @@ NET "PCI_nSERR"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;

-NET "LED_ALIVE"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 6938e3fd728284888fb00e38c55cd28da4370c28..e079bbb5667dc41df3d35ed7bec0d471879327d1 100644 (file)
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -11,7 +11,10 @@ generic (
 port (
        clk_i : in std_logic;
        nrst_i : in std_logic;
 port (
        clk_i : in std_logic;
        nrst_i : in std_logic;

-       led_o : out std_logic
+       led2_o : out std_logic;
+       led3_o : out std_logic;
+       led4_o : out std_logic;
+       led5_o : out std_logic

 );   
 
 end heartbeat;
 );   
 
 end heartbeat;


@@ -28,7 +31,10 @@ if (clk_i'event AND clk_i = '1') then
        if nrst_i = '0' then
                counter := (others => '0');
         else
        if nrst_i = '0' then
                counter := (others => '0');
         else

-               led_o <= state;
+               led5_o <= state;
+               led2_o <= state;
+               led4_o <= not state;
+               led3_o <= not state;

                counter := counter + 1;
                if counter = divider then
                        state := not state;
                counter := counter + 1;
                if counter = divider then
                        state := not state;

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 283495995ddebc28b886d24c23870a0316705b0b..b0739895d536833d7a1a5db286d478bb755cade8 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -60,9 +60,10 @@ port (
     PCI_nINT    : out std_logic;\r
  \r
        -- debug signals\r
     PCI_nINT    : out std_logic;\r
  \r
        -- debug signals\r

-       LED_INIT         : out std_logic;\r
-       LED_ACCESS       : out std_logic;\r
-       LED_ALIVE : out std_logic\r
+       LED3    : out std_logic;\r
+       LED2    : out std_logic;\r
+       LED4            : out std_logic;\r
+       LED5            : out std_logic\r

 \r
 );\r
 end raggedstone;\r
 \r
 );\r
 end raggedstone;\r


@@ -123,7 +124,10 @@ component heartbeat
 port (\r
        clk_i : in std_logic;\r
        nrst_i : in std_logic;\r
 port (\r
        clk_i : in std_logic;\r
        nrst_i : in std_logic;\r

-       led_o : out std_logic\r
+       led2_o : out std_logic;\r
+       led3_o : out std_logic;\r
+       led4_o : out std_logic;\r
+       led5_o : out std_logic\r

 );\r
 end component;\r
 \r
 );\r
 end component;\r
 \r


@@ -178,9 +182,9 @@ port map(
                wb_cyc_o =>             wb_cyc,\r
                wb_ack_i =>             wb_ack,\r
                wb_err_i =>             wb_err,\r
                wb_cyc_o =>             wb_cyc,\r
                wb_ack_i =>             wb_ack,\r
                wb_err_i =>             wb_err,\r

-               wb_int_i =>             wb_int,\r
-               debug_init =>   LED_INIT,\r
-               debug_access => LED_ACCESS\r
+               wb_int_i =>             wb_int\r
+--             debug_init =>   LED3,\r
+--             debug_access => LED2\r

                );\r
 \r
 --+-----------------------------------------+\r
                );\r
 \r
 --+-----------------------------------------+\r


@@ -191,7 +195,10 @@ my_heartbeat: component heartbeat
 port map( \r
        clk_i => PCI_CLK,\r
        nrst_i => PCI_nRES,\r
 port map( \r
        clk_i => PCI_CLK,\r
        nrst_i => PCI_nRES,\r

-       led_o => LED_ALIVE\r
+       led2_o => LED2,\r
+       led3_o => LED3,\r
+       led4_o => LED4,\r
+       led5_o => LED5\r

 );\r
 \r
 end raggedstone_arch;\r
 );\r
 \r
 end raggedstone_arch;\r