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cvs.zerfleddert.de Git - raggedstone/log
michael [Tue, 20 Mar 2007 23:32:26 +0000 (23:32 +0000)]
eth_cop
michael [Tue, 20 Mar 2007 23:00:17 +0000 (23:00 +0000)]
put last mac pin on led...
sithglan [Tue, 20 Mar 2007 22:39:24 +0000 (22:39 +0000)]
WISHBONE B3
sithglan [Tue, 20 Mar 2007 22:17:38 +0000 (22:17 +0000)]
+= use xilinx block ram for ethernet
sithglan [Tue, 20 Mar 2007 21:13:03 +0000 (21:13 +0000)]
+= ignore
sithglan [Tue, 20 Mar 2007 21:10:18 +0000 (21:10 +0000)]
we have pci device
sithglan [Tue, 20 Mar 2007 20:56:19 +0000 (20:56 +0000)]
changes
sithglan [Tue, 20 Mar 2007 20:33:59 +0000 (20:33 +0000)]
progress
sithglan [Tue, 20 Mar 2007 17:50:56 +0000 (17:50 +0000)]
add shit
michael [Tue, 20 Mar 2007 15:26:44 +0000 (15:26 +0000)]
use internal clock
michael [Mon, 19 Mar 2007 20:56:08 +0000 (20:56 +0000)]
it builds, lets ship it
sithglan [Mon, 19 Mar 2007 16:44:04 +0000 (16:44 +0000)]
lot of new files
michael [Sun, 18 Mar 2007 14:49:10 +0000 (14:49 +0000)]
UseHighz for programming the spartan 3, as programming via parallel cable
will else fail on ise 9.1
michael [Wed, 14 Mar 2007 09:43:12 +0000 (09:43 +0000)]
create device node
michael [Sun, 11 Mar 2007 23:21:32 +0000 (23:21 +0000)]
revert previous Makefile commit, delete *.cdc files, too
michael [Sun, 11 Mar 2007 23:19:47 +0000 (23:19 +0000)]
working vio
it's now possible to send interrupts from within chipscope
michael [Sun, 11 Mar 2007 15:45:01 +0000 (15:45 +0000)]
watch vio out on LED
michael [Sun, 11 Mar 2007 15:30:24 +0000 (15:30 +0000)]
add cable help
michael [Sun, 11 Mar 2007 15:29:00 +0000 (15:29 +0000)]
add vio to trigger an interrupt from chipscope (doesn't work currently, but
doesn't harm either)
sithglan [Sun, 11 Mar 2007 13:57:30 +0000 (13:57 +0000)]
more to ignore
sithglan [Sun, 11 Mar 2007 13:54:36 +0000 (13:54 +0000)]
md5sum
michael [Sun, 11 Mar 2007 13:29:16 +0000 (13:29 +0000)]
rename ports
sithglan [Sun, 11 Mar 2007 13:28:49 +0000 (13:28 +0000)]
load driver automatically if not loaded
sithglan [Sun, 11 Mar 2007 13:23:11 +0000 (13:23 +0000)]
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
michael [Sun, 11 Mar 2007 13:13:04 +0000 (13:13 +0000)]
interrupt
michael [Sun, 11 Mar 2007 12:59:40 +0000 (12:59 +0000)]
PCI_IDSEL as trigger
sithglan [Sun, 11 Mar 2007 12:46:04 +0000 (12:46 +0000)]
test target
michael [Sun, 11 Mar 2007 12:40:31 +0000 (12:40 +0000)]
bugfix
michael [Sun, 11 Mar 2007 12:32:35 +0000 (12:32 +0000)]
IDSEL
sithglan [Sun, 11 Mar 2007 12:24:35 +0000 (12:24 +0000)]
rollback
sithglan [Sun, 11 Mar 2007 11:59:56 +0000 (11:59 +0000)]
get rid of vergleich
sithglan [Sun, 11 Mar 2007 11:35:10 +0000 (11:35 +0000)]
this file is no longer autogenerated
sithglan [Sun, 11 Mar 2007 11:34:00 +0000 (11:34 +0000)]
cleanup config space
sithglan [Sun, 11 Mar 2007 11:25:01 +0000 (11:25 +0000)]
more merging
sithglan [Sun, 11 Mar 2007 11:18:43 +0000 (11:18 +0000)]
gone
sithglan [Sun, 11 Mar 2007 11:16:52 +0000 (11:16 +0000)]
even more consolidation
sithglan [Sun, 11 Mar 2007 11:10:24 +0000 (11:10 +0000)]
consolidate more
sithglan [Sun, 11 Mar 2007 11:00:19 +0000 (11:00 +0000)]
etnerprise level consolidation
sithglan [Sun, 11 Mar 2007 10:54:47 +0000 (10:54 +0000)]
merge config space
sithglan [Sun, 11 Mar 2007 10:50:27 +0000 (10:50 +0000)]
begin to merge confi space
sithglan [Sun, 11 Mar 2007 10:45:29 +0000 (10:45 +0000)]
shut the fuck up
michael [Sun, 11 Mar 2007 10:32:44 +0000 (10:32 +0000)]
really fix deps
michael [Sun, 11 Mar 2007 10:19:25 +0000 (10:19 +0000)]
fix dependencies
sithglan [Sun, 11 Mar 2007 09:14:58 +0000 (09:14 +0000)]
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
sithglan [Sun, 11 Mar 2007 09:05:56 +0000 (09:05 +0000)]
Adding a test bench back that isn't a test bench. I shouldn't have deleted in
the first place because all real testbenches were gone by yesterday.
sithglan [Sun, 11 Mar 2007 08:55:29 +0000 (08:55 +0000)]
all files to lowercase,
move everything except par/ser and ser/par into pci
sithglan [Sun, 11 Mar 2007 08:47:55 +0000 (08:47 +0000)]
move config space header into pci core directory
sithglan [Sun, 11 Mar 2007 08:44:31 +0000 (08:44 +0000)]
identing
sithglan [Sun, 11 Mar 2007 08:21:24 +0000 (08:21 +0000)]
coding style
sithglan [Sun, 11 Mar 2007 08:16:41 +0000 (08:16 +0000)]
move, ident
sithglan [Sun, 11 Mar 2007 08:04:56 +0000 (08:04 +0000)]
dos2unix *.vhd
sithglan [Sun, 11 Mar 2007 08:02:23 +0000 (08:02 +0000)]
move address register
michael [Sun, 11 Mar 2007 01:03:41 +0000 (01:03 +0000)]
name ports
michael [Sun, 11 Mar 2007 00:52:26 +0000 (00:52 +0000)]
more LA signals
michael [Sun, 11 Mar 2007 00:28:00 +0000 (00:28 +0000)]
add analyzer target
michael [Sat, 10 Mar 2007 23:24:03 +0000 (23:24 +0000)]
add PCI_nREQ
sithglan [Sat, 10 Mar 2007 22:37:00 +0000 (22:37 +0000)]
+= userland
sithglan [Sat, 10 Mar 2007 22:35:54 +0000 (22:35 +0000)]
+= driver
michael [Sat, 10 Mar 2007 21:42:59 +0000 (21:42 +0000)]
cleaner
michael [Sat, 10 Mar 2007 21:39:33 +0000 (21:39 +0000)]
cleanup after coregen
michael [Sat, 10 Mar 2007 21:36:33 +0000 (21:36 +0000)]
missing renames...
michael [Sat, 10 Mar 2007 21:35:08 +0000 (21:35 +0000)]
rename fifo to dhwk_fifo
michael [Sat, 10 Mar 2007 21:30:57 +0000 (21:30 +0000)]
don't rewrite .xco all the time
michael [Sat, 10 Mar 2007 21:27:01 +0000 (21:27 +0000)]
make clean makes really clean now
michael [Sat, 10 Mar 2007 21:23:22 +0000 (21:23 +0000)]
remove build fifo, ila and icon
add rules to build fifo, ila and icon
michael [Sat, 10 Mar 2007 19:59:18 +0000 (19:59 +0000)]
chipscope
michael [Sat, 10 Mar 2007 19:12:33 +0000 (19:12 +0000)]
trigger
sithglan [Sat, 10 Mar 2007 18:52:50 +0000 (18:52 +0000)]
cleanup
sithglan [Sat, 10 Mar 2007 18:36:37 +0000 (18:36 +0000)]
code cleanup
michael [Sat, 10 Mar 2007 18:27:12 +0000 (18:27 +0000)]
CBEn
michael [Sat, 10 Mar 2007 18:08:57 +0000 (18:08 +0000)]
larger ila
michael [Sat, 10 Mar 2007 18:01:41 +0000 (18:01 +0000)]
level
michael [Sat, 10 Mar 2007 16:58:57 +0000 (16:58 +0000)]
updated chipscope project
michael [Sat, 10 Mar 2007 16:45:55 +0000 (16:45 +0000)]
-fifo_control stuff
michael [Sat, 10 Mar 2007 16:41:30 +0000 (16:41 +0000)]
irgendwie gehts
michael [Sat, 10 Mar 2007 16:08:48 +0000 (16:08 +0000)]
now we only lose half the bytes
michael [Sat, 10 Mar 2007 15:48:06 +0000 (15:48 +0000)]
other watched signals
sithglan [Sat, 10 Mar 2007 14:57:28 +0000 (14:57 +0000)]
interrupt scheisse
michael [Sat, 10 Mar 2007 14:13:22 +0000 (14:13 +0000)]
not not
michael [Sat, 10 Mar 2007 14:07:35 +0000 (14:07 +0000)]
chipscope
michael [Sat, 10 Mar 2007 13:36:55 +0000 (13:36 +0000)]
?
michael [Sat, 10 Mar 2007 12:54:21 +0000 (12:54 +0000)]
invert interrupt
michael [Sat, 10 Mar 2007 12:40:33 +0000 (12:40 +0000)]
loopback
michael [Sat, 10 Mar 2007 12:34:55 +0000 (12:34 +0000)]
fifo
michael [Sat, 10 Mar 2007 11:44:33 +0000 (11:44 +0000)]
add ven_rev_id
sithglan [Sat, 10 Mar 2007 11:42:23 +0000 (11:42 +0000)]
*** empty log message ***
michael [Sat, 10 Mar 2007 11:40:16 +0000 (11:40 +0000)]
ucf
michael [Sat, 10 Mar 2007 11:27:06 +0000 (11:27 +0000)]
it synthesizes
sithglan [Sat, 10 Mar 2007 11:24:03 +0000 (11:24 +0000)]
first import of dhwk.
michael [Thu, 8 Mar 2007 22:00:53 +0000 (22:00 +0000)]
connect LEDs on IDE board to main FPGA and let them blink
michael [Mon, 5 Mar 2007 22:59:59 +0000 (22:59 +0000)]
add sources for ide daughterboard cpld
contains a complete ucf
also a sample vhdl file which lights 3 of the 4 leds
michael [Sat, 3 Mar 2007 10:40:32 +0000 (10:40 +0000)]
use rising_edge(clk_i)
michael [Sun, 25 Feb 2007 11:25:33 +0000 (11:25 +0000)]
make load DRIVER=/home/michael/Raggedstone/usb-driver/libusb-driver.so
works now
sithglan [Wed, 14 Feb 2007 20:20:24 +0000 (20:20 +0000)]
+= Installationsanweisungen
michael [Tue, 13 Feb 2007 22:43:44 +0000 (22:43 +0000)]
running light ;-)
michael [Sun, 11 Feb 2007 22:49:18 +0000 (22:49 +0000)]
we_o
michael [Sun, 11 Feb 2007 22:48:28 +0000 (22:48 +0000)]
first error fixed
michael [Sun, 11 Feb 2007 22:45:55 +0000 (22:45 +0000)]
verdrahtung
sithglan [Sun, 11 Feb 2007 22:44:16 +0000 (22:44 +0000)]
do something with the fifo stuff
sithglan [Sun, 11 Feb 2007 22:37:27 +0000 (22:37 +0000)]
typos
projects / raggedstone / log