]> cvs.zerfleddert.de Git - raggedstone/shortlog
raggedstone
2007-03-11 sithglanmd5sum
2007-03-11 michaelrename ports
2007-03-11 sithglanload driver automatically if not loaded
2007-03-11 sithglanperl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1...
2007-03-11 michaelinterrupt
2007-03-11 michaelPCI_IDSEL as trigger
2007-03-11 sithglantest target
2007-03-11 michaelbugfix
2007-03-11 michaelIDSEL
2007-03-11 sithglanrollback
2007-03-11 sithglanget rid of vergleich
2007-03-11 sithglanthis file is no longer autogenerated
2007-03-11 sithglancleanup config space
2007-03-11 sithglanmore merging
2007-03-11 sithglangone
2007-03-11 sithglaneven more consolidation
2007-03-11 sithglanconsolidate more
2007-03-11 sithglanetnerprise level consolidation
2007-03-11 sithglanmerge config space
2007-03-11 sithglanbegin to merge confi space
2007-03-11 sithglanshut the fuck up
2007-03-11 michaelreally fix deps
2007-03-11 michaelfix dependencies
2007-03-11 sithglanperl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1...
2007-03-11 sithglanAdding a test bench back that isn't a test bench. ...
2007-03-11 sithglanall files to lowercase,
2007-03-11 sithglanmove config space header into pci core directory
2007-03-11 sithglanidenting
2007-03-11 sithglancoding style
2007-03-11 sithglanmove, ident
2007-03-11 sithglandos2unix *.vhd
2007-03-11 sithglanmove address register
2007-03-11 michaelname ports
2007-03-11 michaelmore LA signals
2007-03-11 michaeladd analyzer target
2007-03-10 michaeladd PCI_nREQ
2007-03-10 sithglan+= userland
2007-03-10 sithglan+= driver
2007-03-10 michaelcleaner
2007-03-10 michaelcleanup after coregen
2007-03-10 michaelmissing renames...
2007-03-10 michaelrename fifo to dhwk_fifo
2007-03-10 michaeldon't rewrite .xco all the time
2007-03-10 michaelmake clean makes really clean now
2007-03-10 michaelremove build fifo, ila and icon
2007-03-10 michaelchipscope
2007-03-10 michaeltrigger
2007-03-10 sithglancleanup
2007-03-10 sithglancode cleanup
2007-03-10 michaelCBEn
2007-03-10 michaellarger ila
2007-03-10 michaellevel
2007-03-10 michaelupdated chipscope project
2007-03-10 michael-fifo_control stuff
2007-03-10 michaelirgendwie gehts
2007-03-10 michaelnow we only lose half the bytes
2007-03-10 michaelother watched signals
2007-03-10 sithglaninterrupt scheisse
2007-03-10 michaelnot not
2007-03-10 michaelchipscope
2007-03-10 michael?
2007-03-10 michaelinvert interrupt
2007-03-10 michaelloopback
2007-03-10 michaelfifo
2007-03-10 michaeladd ven_rev_id
2007-03-10 sithglan*** empty log message ***
2007-03-10 michaelucf
2007-03-10 michaelit synthesizes
2007-03-10 sithglanfirst import of dhwk.
2007-03-08 michaelconnect LEDs on IDE board to main FPGA and let them...
2007-03-05 michaeladd sources for ide daughterboard cpld
2007-03-03 michaeluse rising_edge(clk_i)
2007-02-25 michaelmake load DRIVER=/home/michael/Raggedstone/usb-driver...
2007-02-14 sithglan+= Installationsanweisungen
2007-02-13 michaelrunning light ;-)
2007-02-11 michaelwe_o
2007-02-11 michaelfirst error fixed
2007-02-11 michaelverdrahtung
2007-02-11 sithglando something with the fifo stuff
2007-02-11 sithglantypos
2007-02-11 sithglanfifos
2007-02-11 sithglanmore fifo work
2007-02-11 michaelold 7seg thingie
2007-02-11 michael-dpram component
2007-02-11 sithglan-= comments
2007-02-11 michaelfix address width
2007-02-11 sithglanmore infra
2007-02-11 michaelsemicolon
2007-02-11 michaelcomponent for dram
2007-02-11 sithglandefine xilinix and fpga
2007-02-11 sithglanmake it compile
2007-02-11 sithglan+= glue code wb fifo
2007-02-11 sithglan+= interface wb <=> fifo
2007-02-11 michaelfifo component
2007-02-11 sithglan+= dpram
2007-02-11 sithglan+= ignore
2007-02-11 sithglan+= timescale
2007-02-11 michaelfix dependencies
2007-02-11 sithglan+= fifo
2007-02-11 sithglandhwk
next
Impressum, Datenschutz